@@ -3633,6 +3633,34 @@ static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
pipe_config->mso.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
}
+static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 dss1 = 0;
+
+ if (!HAS_MSO(i915))
+ return;
+
+ if (crtc_state->mso.enable) {
+ /* Splitter enable is supported for pipe A only. */
+ if (drm_WARN_ON(&i915->drm, pipe != PIPE_A))
+ return;
+
+ dss1 |= SPLITTER_ENABLE;
+ dss1 |= OVERLAP_PIXELS(crtc_state->mso.pixel_overlap);
+ if (crtc_state->mso.link_count == 2)
+ dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
+ else
+ dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
+ }
+
+ intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
+ SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
+ OVERLAP_PIXELS_MASK, dss1);
+}
+
static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
@@ -3733,6 +3761,11 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
lane_reversal);
}
+ /*
+ * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
+ */
+ intel_ddi_mso_configure(crtc_state);
+
/*
* 7.g Configure and enable DDI_BUF_CTL
* 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
@@ -5614,6 +5647,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
goto err;
dig_port->hpd_pulse = intel_dp_hpd_pulse;
+
+ /* Splitter enable for eDP MSO is supported for pipe A only. */
+ if (dig_port->dp.mso_link_count)
+ encoder->pipe_mask = BIT(PIPE_A);
}
/* In theory we don't need the encoder->type check, but leave it just in
@@ -1759,6 +1759,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
int ret = 0, output_bpp;
+ if (intel_dp->mso_link_count) {
+ pipe_config->mso.enable = true;
+ pipe_config->mso.link_count = intel_dp->mso_link_count;
+ /* FIXME: Read this from DisplayID 2.0 */
+ pipe_config->mso.pixel_overlap = 0;
+ }
+
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
pipe_config->has_pch_encoder = true;
@@ -3561,8 +3568,10 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp)
if (mso) {
drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n",
mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso);
- drm_err(&i915->drm, "No source MSO support, disabling\n");
- mso = 0;
+ if (!HAS_MSO(i915)) {
+ drm_err(&i915->drm, "No source MSO support, disabling\n");
+ mso = 0;
+ }
}
intel_dp->mso_link_count = mso;
If the source and sink support MSO, enable it during link training. FIXME: We need to parse DisplayID 2.0 for pixel overlap. Assume 0 overlap for now. v2: Limit MSO to pipe A using ->pipe_mask Cc: Nischal Varide <nischal.varide@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 37 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++-- 2 files changed, 48 insertions(+), 2 deletions(-)