@@ -592,7 +592,7 @@ static bool is_enabling(int old, int new, int threshold)
return old < threshold && new >= threshold;
}
-static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
+static int g4x_wm_num_levels(struct drm_i915_private *dev_priv)
{
return dev_priv->display.wm.max_level + 1;
}
@@ -936,7 +936,7 @@ static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
bool dirty = false;
- for (; level < intel_wm_num_levels(dev_priv); level++) {
+ for (; level < g4x_wm_num_levels(dev_priv); level++) {
struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
dirty |= raw->plane[plane_id] != value;
@@ -955,7 +955,7 @@ static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
/* NORMAL level doesn't have an FBC watermark */
level = max(level, G4X_WM_LEVEL_SR);
- for (; level < intel_wm_num_levels(dev_priv); level++) {
+ for (; level < g4x_wm_num_levels(dev_priv); level++) {
struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
dirty |= raw->fbc != value;
@@ -974,7 +974,7 @@ static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
+ int num_levels = g4x_wm_num_levels(to_i915(plane->base.dev));
enum plane_id plane_id = plane->id;
bool dirty = false;
int level;
@@ -1534,7 +1534,7 @@ static void vlv_invalidate_wms(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- for (; level < intel_wm_num_levels(dev_priv); level++) {
+ for (; level < g4x_wm_num_levels(dev_priv); level++) {
enum plane_id plane_id;
for_each_plane_id_on_crtc(crtc, plane_id)
@@ -1561,7 +1561,7 @@ static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
int level, enum plane_id plane_id, u16 value)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- int num_levels = intel_wm_num_levels(dev_priv);
+ int num_levels = g4x_wm_num_levels(dev_priv);
bool dirty = false;
for (; level < num_levels; level++) {
@@ -1580,7 +1580,7 @@ static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum plane_id plane_id = plane->id;
- int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
+ int num_levels = g4x_wm_num_levels(to_i915(plane->base.dev));
int level;
bool dirty = false;
@@ -1648,7 +1648,7 @@ static int _vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
int level;
/* initially allow all levels */
- wm_state->num_levels = intel_wm_num_levels(dev_priv);
+ wm_state->num_levels = g4x_wm_num_levels(dev_priv);
/*
* Note that enabling cxsr with no primary/sprite planes
* enabled can wedge the pipe. Hence we only allow cxsr
@@ -3613,7 +3613,7 @@ static void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
struct intel_plane_state *plane_state =
to_intel_plane_state(plane->base.state);
enum plane_id plane_id = plane->id;
- int level, num_levels = intel_wm_num_levels(dev_priv);
+ int level, num_levels = g4x_wm_num_levels(dev_priv);
if (plane_state->uapi.visible)
continue;
@@ -3768,7 +3768,7 @@ static void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
struct intel_plane_state *plane_state =
to_intel_plane_state(plane->base.state);
enum plane_id plane_id = plane->id;
- int level, num_levels = intel_wm_num_levels(dev_priv);
+ int level, num_levels = g4x_wm_num_levels(dev_priv);
if (plane_state->uapi.visible)
continue;
Rename intel_wm_num_levels() to g4x_wm_num_levels() to make the name available for generic watermark code. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/i9xx_wm.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)