From patchwork Wed Sep 2 05:19:30 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xiang, Haihao" X-Patchwork-Id: 45141 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n825KPxI030993 for ; Wed, 2 Sep 2009 05:20:25 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3BE4F9E996; Tue, 1 Sep 2009 22:20:25 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 7386B9E741 for ; Tue, 1 Sep 2009 22:20:23 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 01 Sep 2009 22:17:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.44,316,1249282800"; d="scan'208";a="723101597" Received: from xhh-945g.sh.intel.com (HELO [10.239.36.160]) ([10.239.36.160]) by fmsmga001.fm.intel.com with ESMTP; 01 Sep 2009 22:23:25 -0700 From: "Xiang, Haihao" To: "intel-gfx@lists.freedesktop.org" In-Reply-To: <1251868296-6595-3-git-send-email-haihao.xiang@intel.com> References: <1251868296-6595-1-git-send-email-haihao.xiang@intel.com> <1251868296-6595-2-git-send-email-haihao.xiang@intel.com> <1251868296-6595-3-git-send-email-haihao.xiang@intel.com> Date: Wed, 02 Sep 2009 13:19:30 +0800 Message-Id: <1251868770.9743.45.camel@xhh-945g> Mime-Version: 1.0 X-Mailer: Evolution 2.22.1 Subject: Re: [Intel-gfx] [PATCH] intel_gpu_dump: add support for IGDNG X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.9 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org On Wed, 2009-09-02 at 13:11 +0800, Xiang, Haihao wrote: > --- > lib/intel_chipset.h | 10 +++++++++- > 1 files changed, 9 insertions(+), 1 deletions(-) > > diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h > index 4593d90..03ba0b2 100755 > --- a/lib/intel_chipset.h > +++ b/lib/intel_chipset.h > @@ -67,6 +67,9 @@ > #define PCI_CHIP_G45_G 0x2E22 > #define PCI_CHIP_G41_G 0x2E32 > > +#define PCI_CHIP_ILD_G 0x0042 > +#define PCI_CHIP_ILM_G 0x0046 > + > #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ > devid == PCI_CHIP_I915_GM || \ > devid == PCI_CHIP_I945_GM || \ > @@ -82,6 +85,10 @@ > #define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM) > #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) > > +#define IS_ILD(devid) (devid == PCI_CHIP_ILD_G) > +#define IS_ILM(devid) (devid == PCI_CHIP_ILM_G) > +#define IS_IGDNG(devid) (IS_ILD(devid) || IS_ILM(devid)) > + > #define IS_915(devid) (devid == PCI_CHIP_I915_G || \ > devid == PCI_CHIP_E7221_G || \ > devid == PCI_CHIP_I915_GM) > @@ -99,7 +106,8 @@ > devid == PCI_CHIP_I965_GM || \ > devid == PCI_CHIP_I965_GME || \ > devid == PCI_CHIP_I946_GZ || \ > - IS_G4X(devid)) > + IS_G4X(devid) || \ > + IS_IGDNG(devid)) > > #define IS_9XX(devid) (IS_915(devid) || \ > IS_945(devid) || \ Need to fix STATE_BASE_ADDRESS output on IGDNG --- lib/intel_chipset.h | 10 +++++++- tools/intel_gpu_dump.c | 58 +++++++++++++++++++++++++++++++++++------------ 2 files changed, 52 insertions(+), 16 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 4593d90..03ba0b2 100755 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -67,6 +67,9 @@ #define PCI_CHIP_G45_G 0x2E22 #define PCI_CHIP_G41_G 0x2E32 +#define PCI_CHIP_ILD_G 0x0042 +#define PCI_CHIP_ILM_G 0x0046 + #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ devid == PCI_CHIP_I915_GM || \ devid == PCI_CHIP_I945_GM || \ @@ -82,6 +85,10 @@ #define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM) #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) +#define IS_ILD(devid) (devid == PCI_CHIP_ILD_G) +#define IS_ILM(devid) (devid == PCI_CHIP_ILM_G) +#define IS_IGDNG(devid) (IS_ILD(devid) || IS_ILM(devid)) + #define IS_915(devid) (devid == PCI_CHIP_I915_G || \ devid == PCI_CHIP_E7221_G || \ devid == PCI_CHIP_I915_GM) @@ -99,7 +106,8 @@ devid == PCI_CHIP_I965_GM || \ devid == PCI_CHIP_I965_GME || \ devid == PCI_CHIP_I946_GZ || \ - IS_G4X(devid)) + IS_G4X(devid) || \ + IS_IGDNG(devid)) #define IS_9XX(devid) (IS_915(devid) || \ IS_945(devid) || \ diff --git a/tools/intel_gpu_dump.c b/tools/intel_gpu_dump.c index 791f497..a5b1b77 100644 --- a/tools/intel_gpu_dump.c +++ b/tools/intel_gpu_dump.c @@ -1472,7 +1472,7 @@ i965_decode_urb_fence(uint32_t *data, uint32_t hw_offset, int len, int count, } static int -decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures) +decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures, uint32_t devid) { unsigned int opcode, len; int i; @@ -1528,9 +1528,11 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures) data[1] >> 6, data[1] & 0x3f); return len; case 0x6101: - if (len != 6) + if ((IS_IGDNG(devid) && len != 8) || + (!IS_IGDNG(devid) && len != 6)) fprintf(out, "Bad count in STATE_BASE_ADDRESS\n"); - if (count < 6) + if ((IS_IGDNG(devid) && count < 8) || + (!IS_IGDNG(devid) && count < 6)) BUFFER_FAIL(count, len, "STATE_BASE_ADDRESS"); instr_out(data, hw_offset, 0, @@ -1554,17 +1556,43 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures) } else instr_out(data, hw_offset, 3, "Indirect state not updated\n"); - if (data[4] & 1) { - instr_out(data, hw_offset, 4, "General state upper bound 0x%08x\n", - data[4] & ~1); - } else - instr_out(data, hw_offset, 4, "General state not updated\n"); - - if (data[5] & 1) { - instr_out(data, hw_offset, 5, "Indirect state upper bound 0x%08x\n", - data[5] & ~1); - } else - instr_out(data, hw_offset, 5, "Indirect state not updated\n"); + if (IS_IGDNG(devid)) { + if (data[4] & 1) { + instr_out(data, hw_offset, 4, "Instruction base address at 0x%08x\n", + data[4] & ~1); + } else + instr_out(data, hw_offset, 4, "Instruction base address not updated\n"); + + if (data[5] & 1) { + instr_out(data, hw_offset, 5, "General state upper bound 0x%08x\n", + data[4] & ~1); + } else + instr_out(data, hw_offset, 5, "General state not updated\n"); + + if (data[6] & 1) { + instr_out(data, hw_offset, 6, "Indirect state upper bound 0x%08x\n", + data[5] & ~1); + } else + instr_out(data, hw_offset, 6, "Indirect state not updated\n"); + + if (data[7] & 1) { + instr_out(data, hw_offset, 7, "Instruction access upper bound 0x%08x\n", + data[5] & ~1); + } else + instr_out(data, hw_offset, 7, "Instruction access upper bound not updated\n"); + } else { + if (data[4] & 1) { + instr_out(data, hw_offset, 4, "General state upper bound 0x%08x\n", + data[4] & ~1); + } else + instr_out(data, hw_offset, 4, "General state not updated\n"); + + if (data[5] & 1) { + instr_out(data, hw_offset, 5, "Indirect state upper bound 0x%08x\n", + data[5] & ~1); + } else + instr_out(data, hw_offset, 5, "Indirect state not updated\n"); + } return len; case 0x7800: @@ -1880,7 +1908,7 @@ intel_decode(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid) case 0x3: if (IS_965(devid)) { index += decode_3d_965(data + index, count - index, - hw_offset + index * 4, &failures); + hw_offset + index * 4, &failures, devid); } else if (IS_9XX(devid)) { index += decode_3d(data + index, count - index, hw_offset + index * 4, &failures);