From patchwork Wed Mar 10 22:44:56 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 84728 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2AMkHHC006496 for ; Wed, 10 Mar 2010 22:46:57 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E7A1B9E935; Wed, 10 Mar 2010 14:45:55 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from orsmga101.jf.intel.com (mga06.intel.com [134.134.136.21]) by gabe.freedesktop.org (Postfix) with ESMTP id A2BB59E9FE for ; Wed, 10 Mar 2010 14:45:41 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 10 Mar 2010 14:42:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.49,616,1262592000"; d="scan'208";a="499618426" Received: from unknown (HELO localhost.localdomain) ([10.255.13.214]) by orsmga002.jf.intel.com with ESMTP; 10 Mar 2010 14:44:57 -0800 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Wed, 10 Mar 2010 22:44:56 +0000 Message-Id: <1268261124-13653-10-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 1.7.0 In-Reply-To: <1268261124-13653-1-git-send-email-chris@chris-wilson.co.uk> References: <1268261124-13653-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 09/37] drm/i915: Only enable the pipe/plane if they is a bound fb. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 10 Mar 2010 22:46:57 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e8b5389..3904d43 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3238,18 +3238,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, /* setup pipeconf */ pipeconf = I915_READ(pipeconf_reg); - /* Set up the display plane register */ - dspcntr = DISPPLANE_GAMMA_ENABLE; - - /* Ironlake's plane is forced to pipe, bit 24 is to - enable color space conversion */ - if (!HAS_PCH_SPLIT(dev)) { - if (pipe == 0) - dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; - else - dspcntr |= DISPPLANE_SEL_PIPE_B; - } - if (pipe == 0 && !IS_I965G(dev)) { /* Enable pixel doubling when the dot clock is > 90% of the (display) * core speed. @@ -3264,7 +3252,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, pipeconf &= ~PIPEACONF_DOUBLE_WIDE; } - dspcntr |= DISPLAY_PLANE_ENABLE; pipeconf |= PIPEACONF_ENABLE; dpll |= DPLL_VCO_ENABLE; @@ -3425,13 +3412,27 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); } - I915_WRITE(dspcntr_reg, dspcntr); - /* Flush the plane changes */ ret = intel_pipe_set_base(crtc, x, y, old_fb); - if ((IS_I965G(dev) || plane == 0)) - intel_update_fbc(crtc, &crtc->mode); + /* And then enable the plane */ + dspcntr = I915_READ(dspcntr_reg); + dspcntr |= DISPPLANE_GAMMA_ENABLE; + if (crtc->fb) + dspcntr |= DISPLAY_PLANE_ENABLE; + else + dspcntr &= ~DISPLAY_PLANE_ENABLE; + + /* Ironlake's plane is forced to pipe, bit 24 is to + enable color space conversion */ + if (!HAS_PCH_SPLIT(dev)) { + if (pipe == 0) + dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; + else + dspcntr |= DISPPLANE_SEL_PIPE_B; + } + + I915_WRITE(dspcntr_reg, dspcntr); intel_update_watermarks(dev);