From patchwork Thu Mar 11 15:58:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 84944 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2BFxJ85010736 for ; Thu, 11 Mar 2010 15:59:59 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EA9AE9F694; Thu, 11 Mar 2010 07:59:06 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail.ffwll.ch (cable-static-49-187.intergga.ch [157.161.49.187]) by gabe.freedesktop.org (Postfix) with ESMTP id 098C39F72D for ; Thu, 11 Mar 2010 07:59:04 -0800 (PST) Received: by mail.ffwll.ch (Postfix, from userid 1000) id 4203E20C221; Thu, 11 Mar 2010 16:59:03 +0100 (CET) X-Spam-ASN: X-Spam-Checker-Version: SpamAssassin 3.2.5 (2008-06-10) on orange.ffwll.ch X-Spam-Level: X-Spam-Hammy: 0.000-+--struct, 0.000-+--100644, 0.000-+--signed-off-by X-Spam-Status: No, score=-4.4 required=6.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham version=3.2.5 X-Spam-Spammy: Received: from biene (unknown [192.168.23.129]) by mail.ffwll.ch (Postfix) with ESMTP id 553D320C224; Thu, 11 Mar 2010 16:58:36 +0100 (CET) Received: from daniel by biene with local (Exim 4.71) (envelope-from ) id 1Npkmv-00038v-1c; Thu, 11 Mar 2010 16:59:05 +0100 From: Daniel Vetter To: intel-gfx@lists.freedesktop.org Date: Thu, 11 Mar 2010 16:58:55 +0100 Message-Id: <1268323140-12006-11-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: <1268323140-12006-1-git-send-email-daniel.vetter@ffwll.ch> References: <1268323140-12006-1-git-send-email-daniel.vetter@ffwll.ch> Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 10/15] drm/i915: track gpu fence usage more precisely X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 11 Mar 2010 15:59:59 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index db44e61..c32b60c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -128,6 +128,7 @@ struct drm_i915_master_private { struct drm_i915_fence_reg { struct drm_gem_object *obj; + uint32_t last_rendering_seqno; struct list_head lru_list; }; @@ -652,13 +653,45 @@ struct drm_i915_gem_object { * (has pending rendering), and is not set if it's on inactive (ready * to be unbound). */ - int active; + int active : 1; /** * This is set if the object has been written to since last bound * to the GTT */ - int dirty; + int dirty : 1; + + /** + * Used for checking the object doesn't appear more than once + * in an execbuffer object list. + */ + int in_execbuffer : 1; + + /** + * This is set when the most recent request using this object needs a + * fence. Used to decide whether to update fence lru and seqno when + * flushing gpu writes. + */ + int fenced_gpu_access : 1; + + /** + * Used in do_execbuffer to update fenced_gpu_access when the execbuffer + * can be executed. + */ + int current_execbuffer_needs_fencing : 1; + + /** + * Fence register bits (if any) for this object. Will be set + * as needed when mapped into the GTT. + * Protected by dev->struct_mutex. + * Size: 16 fences + sign (for FENCE_REG_NONE): 5 bits + */ + int fence_reg : 5; + + /** + * Advice: are the backing pages purgeable? + */ + int madv : 3; /** AGP memory structure for our GTT binding. */ DRM_AGP_MEM *agp_mem; @@ -678,13 +711,6 @@ struct drm_i915_gem_object { */ uint64_t mmap_offset; - /** - * Fence register bits (if any) for this object. Will be set - * as needed when mapped into the GTT. - * Protected by dev->struct_mutex. - */ - int fence_reg; - /** How many users have pinned this object in GTT space */ int pin_count; @@ -715,17 +741,6 @@ struct drm_i915_gem_object { struct drm_i915_gem_phys_object *phys_obj; /** - * Used for checking the object doesn't appear more than once - * in an execbuffer object list. - */ - int in_execbuffer; - - /** - * Advice: are the backing pages purgeable? - */ - int madv; - - /** * Number of crtcs where this object is currently the fb, but * will be page flipped away on the next vblank. When it * reaches 0, dev_priv->pending_flip_queue will be woken up. diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 4eeed4e..5183fdd 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1515,10 +1515,31 @@ i915_gem_object_move_to_active(struct drm_gem_object *obj) list_move_tail(&obj_priv->list, &dev_priv->mm.active_list); spin_unlock(&dev_priv->mm.active_list_lock); + + if (obj_priv->fenced_gpu_access) { + struct drm_i915_fence_reg *reg = + &dev_priv->fence_regs[obj_priv->fence_reg]; + reg->last_rendering_seqno = seqno; + } obj_priv->last_rendering_seqno = seqno; } static void +i915_gem_object_move_off_active(struct drm_gem_object *obj) +{ + struct drm_device *dev = obj->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + struct drm_i915_gem_object *obj_priv = obj->driver_private; + + obj_priv->last_rendering_seqno = 0; + if (obj_priv->fenced_gpu_access) { + struct drm_i915_fence_reg *reg = + &dev_priv->fence_regs[obj_priv->fence_reg]; + reg->last_rendering_seqno = 0; + } +} + +static void i915_gem_object_move_to_flushing(struct drm_gem_object *obj) { struct drm_device *dev = obj->dev; @@ -1527,7 +1548,7 @@ i915_gem_object_move_to_flushing(struct drm_gem_object *obj) BUG_ON(!obj_priv->active); list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); - obj_priv->last_rendering_seqno = 0; + i915_gem_object_move_off_active(obj); } /* Immediately discard the backing storage */ @@ -1565,7 +1586,9 @@ i915_gem_object_move_to_inactive(struct drm_gem_object *obj) BUG_ON(!list_empty(&obj_priv->gpu_write_list)); - obj_priv->last_rendering_seqno = 0; + i915_gem_object_move_off_active(obj); + obj_priv->fenced_gpu_access = 0; + if (obj_priv->active) { obj_priv->active = 0; drm_gem_object_unreference(obj); @@ -3325,7 +3348,9 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, i915_gem_object_unpin(obj); return ret; } - } + obj_priv->current_execbuffer_needs_fencing = 1; + } else + obj_priv->current_execbuffer_needs_fencing = 0; entry->offset = obj_priv->gtt_offset; @@ -3990,6 +4015,12 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, */ for (i = 0; i < args->buffer_count; i++) { struct drm_gem_object *obj = object_list[i]; + struct drm_i915_gem_object *obj_priv = obj->driver_private; + + if (obj_priv->current_execbuffer_needs_fencing) + obj_priv->fenced_gpu_access = 1; + else + obj_priv->fenced_gpu_access = 0; i915_gem_object_move_to_active(obj); #if WATCH_LRU @@ -4011,6 +4042,7 @@ err: if (object_list[i]) { obj_priv = object_list[i]->driver_private; obj_priv->in_execbuffer = false; + obj_priv->current_execbuffer_needs_fencing = 0; } drm_gem_object_unreference(object_list[i]); }