@@ -2643,8 +2643,8 @@ int
i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
int pipelined)
{
- struct drm_device *dev = obj->dev;
struct drm_i915_gem_object *obj_priv = obj->driver_private;
+ int ret;
if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
return 0;
@@ -2655,18 +2655,24 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
*/
i915_gem_release_mmap(obj);
- /* On the i915, GPU access to tiled buffers is via a fence,
- * therefore we must wait for any outstanding access to complete
- * before clearing the fence.
- */
- if (!IS_I965G(dev)) {
- int ret;
-
- ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined);
+ if (obj_priv->fenced_gpu_access) {
+ ret = i915_gem_object_flush_gpu_write_domain(obj, 1);
if (ret != 0)
return ret;
}
+ if (!pipelined) {
+ struct drm_device *dev = obj->dev;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ struct drm_i915_fence_reg *reg =
+ &dev_priv->fence_regs[obj_priv->fence_reg];
+ if (reg->last_rendering_seqno != 0) {
+ ret = i915_wait_request(dev, reg->last_rendering_seqno);
+ if (ret != 0)
+ return ret;
+ }
+ }
+
i915_gem_object_flush_gtt_write_domain(obj);
i915_gem_clear_fence_reg(obj, pipelined);