@@ -36,7 +36,8 @@
#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
-static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
+static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
+ int pipelined);
static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
@@ -2628,8 +2629,7 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
if (!IS_I965G(dev)) {
int ret;
- i915_gem_object_flush_gpu_write_domain(obj);
- ret = i915_gem_object_wait_rendering(obj);
+ ret = i915_gem_object_flush_gpu_write_domain(obj, 0);
if (ret != 0)
return ret;
}
@@ -2770,24 +2770,27 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
}
/** Flushes any GPU write domain for the object if it's dirty. */
-static void
-i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
+static int
+i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
+ int pipelined)
{
struct drm_device *dev = obj->dev;
uint32_t old_write_domain;
- if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
- return;
+ if ((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0) {
+ old_write_domain = obj->write_domain;
+ i915_gem_flush(dev, 0, obj->write_domain);
+ BUG_ON(obj->write_domain);
- /* Queue the GPU write cache flushing we need. */
- old_write_domain = obj->write_domain;
- i915_gem_flush(dev, 0, obj->write_domain);
- (void) i915_add_request(dev, NULL);
- BUG_ON(obj->write_domain);
+ trace_i915_gem_object_change_domain(obj,
+ obj->read_domains,
+ old_write_domain);
+ }
- trace_i915_gem_object_change_domain(obj,
- obj->read_domains,
- old_write_domain);
+ if (pipelined)
+ return 0;
+
+ return i915_gem_object_wait_rendering(obj);
}
/** Flushes the GTT write domain for the object if it's dirty. */
@@ -2842,7 +2845,7 @@ i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
i915_gem_object_flush_cpu_write_domain(obj);
break;
default:
- i915_gem_object_flush_gpu_write_domain(obj);
+ i915_gem_object_flush_gpu_write_domain(obj, 1);
break;
}
}
@@ -2864,9 +2867,7 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
if (obj_priv->gtt_space == NULL)
return -EINVAL;
- i915_gem_object_flush_gpu_write_domain(obj);
- /* Wait on any GPU rendering and flushing to occur. */
- ret = i915_gem_object_wait_rendering(obj);
+ ret = i915_gem_object_flush_gpu_write_domain(obj, 0);
if (ret != 0)
return ret;
@@ -2913,9 +2914,7 @@ i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
if (obj_priv->gtt_space == NULL)
return -EINVAL;
- i915_gem_object_flush_gpu_write_domain(obj);
- /* Wait on any GPU rendering and flushing to occur. */
- ret = i915_gem_object_wait_rendering(obj);
+ ret = i915_gem_object_flush_gpu_write_domain(obj, 0);
if (ret != 0)
return ret;
@@ -2953,9 +2952,7 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
uint32_t old_write_domain, old_read_domains;
int ret;
- i915_gem_object_flush_gpu_write_domain(obj);
- /* Wait on any GPU rendering and flushing to occur. */
- ret = i915_gem_object_wait_rendering(obj);
+ ret = i915_gem_object_flush_gpu_write_domain(obj, 0);
if (ret != 0)
return ret;
@@ -3243,9 +3240,7 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
if (offset == 0 && size == obj->size)
return i915_gem_object_set_to_cpu_domain(obj, 0);
- i915_gem_object_flush_gpu_write_domain(obj);
- /* Wait on any GPU rendering and flushing to occur. */
- ret = i915_gem_object_wait_rendering(obj);
+ ret = i915_gem_object_flush_gpu_write_domain(obj, 0);
if (ret != 0)
return ret;
i915_gem_object_flush_gtt_write_domain(obj);