From patchwork Sun Apr 11 13:38:23 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 91914 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3BDbesK026059 for ; Sun, 11 Apr 2010 13:38:15 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D573A9E95C; Sun, 11 Apr 2010 06:37:37 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from localhost.localdomain (cable-static-49-187.intergga.ch [157.161.49.187]) by gabe.freedesktop.org (Postfix) with ESMTP id C0A809E7C2 for ; Sun, 11 Apr 2010 06:37:33 -0700 (PDT) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by localhost.localdomain (8.14.3/8.14.3) with ESMTP id o3BDcTdD004614; Sun, 11 Apr 2010 15:38:29 +0200 Received: (from daniel@localhost) by localhost.localdomain (8.14.3/8.14.3/Submit) id o3BDcTkT004613; Sun, 11 Apr 2010 15:38:29 +0200 From: Daniel Vetter To: intel-gfx@lists.freedesktop.org Date: Sun, 11 Apr 2010 15:38:23 +0200 Message-Id: <1270993104-4568-3-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: <1270993104-4568-1-git-send-email-daniel.vetter@ffwll.ch> References: <1270993104-4568-1-git-send-email-daniel.vetter@ffwll.ch> Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 2/3] i915 render: use tiling bits where possible X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 11 Apr 2010 13:38:16 +0000 (UTC) diff --git a/src/i915_render.c b/src/i915_render.c index 819b963..98b5b88 100644 --- a/src/i915_render.c +++ b/src/i915_render.c @@ -275,7 +275,7 @@ static Bool i915_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit) intel_screen_private *intel = intel_get_screen_private(scrn); uint32_t format, pitch, filter; int w, h, i; - uint32_t wrap_mode; + uint32_t wrap_mode, tiling_bits; pitch = intel_get_pixmap_pitch(pixmap); w = picture->pDrawable->width; @@ -328,10 +328,18 @@ static Bool i915_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit) } /* offset filled in at emit time */ + if (i830_pixmap_tiled(pixmap)) { + tiling_bits = MS3_TILED_SURFACE; + if (i830_get_pixmap_intel(pixmap)->tiling + == I915_TILING_Y) + tiling_bits |= MS3_TILE_WALK; + } else + tiling_bits = 0; + intel->texture[unit] = pixmap; intel->mapstate[unit * 3 + 0] = 0; intel->mapstate[unit * 3 + 1] = format | - MS3_USE_FENCE_REGS | + tiling_bits | ((pixmap->drawable.height - 1) << MS3_HEIGHT_SHIFT) | ((pixmap->drawable.width - 1) << MS3_WIDTH_SHIFT); intel->mapstate[unit * 3 + 2] = ((pitch / 4) - 1) << MS4_PITCH_SHIFT; @@ -482,7 +490,7 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn) PixmapPtr mask = intel->render_mask; PixmapPtr dest = intel->render_dest; uint32_t dst_format = intel->i915_render_state.dst_format, dst_pitch; - uint32_t blendctl; + uint32_t blendctl, tiling_bits; Bool is_affine_src, is_affine_mask; Bool is_solid_src, is_solid_mask; int tex_count, t; @@ -540,8 +548,16 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn) OUT_BATCH (intel->render_mask_solid); } + if (i830_pixmap_tiled(dest)) { + tiling_bits = BUF_3D_TILED_SURFACE; + if (i830_get_pixmap_intel(dest)->tiling + == I915_TILING_Y) + tiling_bits |= BUF_3D_TILE_WALK_Y; + } else + tiling_bits = 0; + OUT_BATCH(_3DSTATE_BUF_INFO_CMD); - OUT_BATCH(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE | + OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits | BUF_3D_PITCH(dst_pitch)); OUT_RELOC_PIXMAP(dest, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);