From patchwork Sat Jun 12 06:32:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhenyu Wang X-Patchwork-Id: 105709 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5C6YGj1017568 for ; Sat, 12 Jun 2010 06:34:52 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 36F1F9E9A6 for ; Fri, 11 Jun 2010 23:34:16 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 898209E9A6 for ; Fri, 11 Jun 2010 23:32:37 -0700 (PDT) Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga102.ch.intel.com with ESMTP; 11 Jun 2010 23:32:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.53,407,1272870000"; d="scan'208";a="288067718" Received: from ubuntu-hp.sh.intel.com (HELO localhost.localdomain) ([10.239.36.43]) by azsmga001.ch.intel.com with ESMTP; 11 Jun 2010 23:32:35 -0700 From: Zhenyu Wang To: eric@anholt.net Date: Sat, 12 Jun 2010 14:32:24 +0800 Message-Id: <1276324347-15668-5-git-send-email-zhenyuw@linux.intel.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1276324347-15668-1-git-send-email-zhenyuw@linux.intel.com> References: <1276324347-15668-1-git-send-email-zhenyuw@linux.intel.com> Cc: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 4/7] drm/i915: Fix fifo size for self-refresh watermark on 965G X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 12 Jun 2010 06:34:52 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 64b0a3a..cf41c96 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2099,7 +2099,8 @@ #define I830_FIFO_LINE_SIZE 32 #define G4X_FIFO_SIZE 127 -#define I945_FIFO_SIZE 127 /* 945 & 965 */ +#define I965_FIFO_SIZE 512 +#define I945_FIFO_SIZE 127 #define I915_FIFO_SIZE 95 #define I855GM_FIFO_SIZE 127 /* In cachelines */ #define I830_FIFO_SIZE 95 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2c3377e..43e3710 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2969,10 +2969,10 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock, pixel_size * sr_hdisplay; sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1); DRM_DEBUG("self-refresh entries: %d\n", sr_entries); - srwm = I945_FIFO_SIZE - sr_entries; + srwm = I965_FIFO_SIZE - sr_entries; if (srwm < 0) srwm = 1; - srwm &= 0x3f; + srwm &= 0x1ff; I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); } else { /* Turn off self refresh if both pipes are enabled */