From patchwork Sat Jun 12 08:45:26 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zou, Nanhai" X-Patchwork-Id: 105725 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5C8k11F016089 for ; Sat, 12 Jun 2010 08:46:36 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E71849F024 for ; Sat, 12 Jun 2010 01:46:00 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id D93719E78F for ; Sat, 12 Jun 2010 01:45:52 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 12 Jun 2010 01:42:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.53,407,1272870000"; d="scan'208";a="807269623" Received: from unknown (HELO hdmi.sh.intel.com) ([10.239.36.16]) by fmsmga001.fm.intel.com with ESMTP; 12 Jun 2010 01:45:30 -0700 From: Zou Nan hai To: Eric Anholt , intel-gfx Date: Sat, 12 Jun 2010 16:45:26 +0800 Message-Id: <1276332326-5642-1-git-send-email-nanhai.zou@intel.com> X-Mailer: git-send-email 1.7.1 Subject: [Intel-gfx] [PATCH] fix some intel_ring_begin size X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 12 Jun 2010 08:46:36 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index cea4f1a..9421d1c 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -406,7 +406,7 @@ bsd_ring_add_request(struct drm_device *dev, { u32 seqno; seqno = intel_ring_get_seqno(dev, ring); - intel_ring_begin(dev, ring, 4); + intel_ring_begin(dev, ring, 16); intel_ring_emit(dev, ring, MI_STORE_DWORD_INDEX); intel_ring_emit(dev, ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); @@ -456,7 +456,7 @@ bsd_ring_dispatch_gem_execbuffer(struct drm_device *dev, { uint32_t exec_start; exec_start = (uint32_t) exec_offset + exec->batch_start_offset; - intel_ring_begin(dev, ring, 2); + intel_ring_begin(dev, ring, 8); intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); intel_ring_emit(dev, ring, exec_start); @@ -492,14 +492,14 @@ render_ring_dispatch_gem_execbuffer(struct drm_device *dev, } if (IS_I830(dev) || IS_845G(dev)) { - intel_ring_begin(dev, ring, 4); + intel_ring_begin(dev, ring, 16); intel_ring_emit(dev, ring, MI_BATCH_BUFFER); intel_ring_emit(dev, ring, exec_start | MI_BATCH_NON_SECURE); intel_ring_emit(dev, ring, exec_start + exec_len - 4); intel_ring_emit(dev, ring, 0); } else { - intel_ring_begin(dev, ring, 4); + intel_ring_begin(dev, ring, 16); if (IS_I965G(dev)) { intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START | (2 << 6)