drm/i915: gen4 vs gen5 DISPLAY_FLIP discrepancy?

Commit Message

Chris Wilson Aug. 8, 2010, 11:50 a.m. UTC

None

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bdd04ae..cd606e5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5120,7 +5120,7 @@  static int intel_crtc_page_flip(struct drm_crtc *crtc,
 	offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
 
 	BEGIN_LP_RING(4);
-	if (IS_I965G(dev)) {
+	if (IS_GEN5(dev)) {
 		int pipe = intel_crtc->pipe;
 		u32 pf, pipesrc;
 
@@ -5136,6 +5136,18 @@  static int intel_crtc_page_flip(struct drm_crtc *crtc,
 		pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
 		pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
 		OUT_RING(pf | pipesrc);
+	} else if (IS_I965G(dev)) {
+		int pipe = intel_crtc->pipe;
+		u32 pf, pipesrc;
+
+		OUT_RING(MI_DISPLAY_FLIP |
+			 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
+		OUT_RING(fb->pitch);
+		OUT_RING(obj_priv->gtt_offset| obj_priv->tiling_mode);
+
+		pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
+		pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
+		OUT_RING(pf | pipesrc);
 	} else if (IS_GEN3(dev)) {
 		OUT_RING(MI_DISPLAY_FLIP_I915 |
 			 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));