From patchwork Sun Aug 22 11:05:32 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 122271 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o7MBApwE022593 for ; Sun, 22 Aug 2010 11:11:26 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A9B89EB3F for ; Sun, 22 Aug 2010 04:10:51 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 75EEC9EB1F for ; Sun, 22 Aug 2010 04:06:15 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 22 Aug 2010 04:06:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.56,251,1280732400"; d="scan'208";a="547572217" Received: from unknown (HELO cantiga.alporthouse.com) ([10.255.17.166]) by orsmga002.jf.intel.com with ESMTP; 22 Aug 2010 04:06:13 -0700 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Sun, 22 Aug 2010 12:05:32 +0100 Message-Id: <1282475148-15951-14-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1282475148-15951-1-git-send-email-chris@chris-wilson.co.uk> References: <1282475148-15951-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 13/29] drm/i915: Clear scanline waits after disabling the pipe. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 22 Aug 2010 11:11:26 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 67e3ec1..9dedf36 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -295,6 +295,8 @@ #define RING_VALID_MASK 0x00000001 #define RING_VALID 0x00000001 #define RING_INVALID 0x00000000 +#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ +#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ #define PRB1_TAIL 0x02040 /* 915+ only */ #define PRB1_HEAD 0x02044 /* 915+ only */ #define PRB1_START 0x02048 /* 915+ only */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e57596a..b9c6487 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2412,6 +2412,26 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) } } +/* + * When we disable a pipe, we need to clear any pending scanline wait events + * to avoid hanging the ring, which we assume we are waiting on. + */ +static void intel_clear_scanline_wait(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u32 tmp; + + if (IS_GEN2(dev)) + /* Can't break the hang on i8xx */ + return; + + tmp = I915_READ(PRB0_CTL); + if (tmp & RING_WAIT) { + I915_WRITE(PRB0_CTL, tmp); + POSTING_READ(PRB0_CTL); + } +} + /** * Sets the power management mode of the pipe and plane. */ @@ -2431,7 +2451,8 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) * with multiple pipes prior to enabling to new pipe. * * When switching off the display, make sure the cursor is - * properly hidden prior to disabling the pipe. + * properly hidden and there are no pending waits prior to + * disabling the pipe. */ if (mode == DRM_MODE_DPMS_ON) intel_update_watermarks(dev); @@ -2442,8 +2463,14 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) if (mode == DRM_MODE_DPMS_ON) intel_crtc_update_cursor(crtc); - else + else { + /* XXX Note that this is not a complete solution, but a hack + * to avoid the most frequently hit hang. + */ + intel_clear_scanline_wait(dev); + intel_update_watermarks(dev); + } if (!dev->primary->master) return;