From patchwork Mon Sep 13 22:35:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 176012 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id o8DMZPr1007205 for ; Mon, 13 Sep 2010 22:35:46 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 12F099EADB for ; Mon, 13 Sep 2010 15:35:25 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail.ffwll.ch (cable-static-49-187.intergga.ch [157.161.49.187]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A4BD9EAF6 for ; Mon, 13 Sep 2010 15:33:23 -0700 (PDT) Received: by mail.ffwll.ch (Postfix, from userid 1000) id D09D020C219; Tue, 14 Sep 2010 00:35:44 +0200 (CEST) X-Spam-ASN: X-Spam-Checker-Version: SpamAssassin 3.2.5 (2008-06-10) on orange.ffwll.ch X-Spam-Level: X-Spam-Hammy: 0.000-+--H*UA:git-send-email, 0.000-+--H*x:git-send-email, 0.000-+--1.7.1 X-Spam-Status: No, score=-4.4 required=6.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham version=3.2.5 X-Spam-Spammy: Received: from viiv.ffwll.ch (viiv.ffwll.ch [192.168.23.128]) by mail.ffwll.ch (Postfix) with ESMTP id 2A52C20C224; Tue, 14 Sep 2010 00:35:24 +0200 (CEST) Received: from daniel by viiv.ffwll.ch with local (Exim 4.72) (envelope-from ) id 1OvHcS-0008MQ-0L; Tue, 14 Sep 2010 00:35:24 +0200 From: Daniel Vetter To: intel-gfx@lists.freedesktop.org Date: Tue, 14 Sep 2010 00:35:01 +0200 Message-Id: <1284417314-32070-5-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1284417314-32070-1-git-send-email-daniel.vetter@ffwll.ch> References: <1284417314-32070-1-git-send-email-daniel.vetter@ffwll.ch> Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 04/17] intel-gtt: introduce pte write function for gen6 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Mon, 13 Sep 2010 22:35:46 +0000 (UTC) diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index 89dcc0b..9292b62 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -1233,27 +1233,6 @@ static void intel_i9xx_setup_flush(void) "can't ioremap flush page - no chipset flushing\n"); } -static int intel_i9xx_configure(void) -{ - int i; - - intel_enable_gtt(); - - agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; - - if (agp_bridge->driver->needs_scratch_page) { - for (i = intel_private.base.gtt_stolen_entries; i < - intel_private.base.gtt_total_entries; i++) { - writel(agp_bridge->scratch_page, intel_private.gtt+i); - } - readl(intel_private.gtt+i-1); /* PCI Posting. */ - } - - global_cache_flush(); - - return 0; -} - static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) { if (intel_private.i9xx_flush_page) @@ -1343,6 +1322,30 @@ static void i965_write_entry(dma_addr_t addr, unsigned int entry, writel(addr | I810_PTE_VALID, intel_private.gtt + entry); } +static void gen6_write_entry(dma_addr_t addr, unsigned int entry, + unsigned int flags) +{ + unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; + unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; + u32 pte_flags; + + if (type_mask == AGP_USER_UNCACHED_MEMORY) + pte_flags = GEN6_PTE_UNCACHED; + else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { + pte_flags = GEN6_PTE_LLC; + if (gfdt) + pte_flags |= GEN6_PTE_GFDT; + } else { /* set 'normal'/'cached' to LLC by default */ + pte_flags = GEN6_PTE_LLC_MLC; + if (gfdt) + pte_flags |= GEN6_PTE_GFDT; + } + + /* gen6 has bit11-4 for physical addr bit39-32 */ + addr |= (addr >> 28) & 0xff0; + writel(addr | pte_flags, intel_private.gtt + entry); +} + static int i9xx_setup(void) { u32 reg_addr; @@ -1535,7 +1538,7 @@ static const struct agp_bridge_driver intel_gen6_driver = { .size_type = FIXED_APER_SIZE, .num_aperture_sizes = 4, .needs_scratch_page = true, - .configure = intel_i9xx_configure, + .configure = intel_fake_agp_configure, .fetch_size = intel_fake_agp_fetch_size, .cleanup = intel_gtt_cleanup, .mask_memory = intel_gen6_mask_memory, @@ -1637,6 +1640,7 @@ static const struct intel_gtt_driver ironlake_gtt_driver = { static const struct intel_gtt_driver sandybridge_gtt_driver = { .gen = 6, .setup = i9xx_setup, + .write_entry = gen6_write_entry, }; /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of