From patchwork Mon Nov 1 05:23:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zou, Nanhai" X-Patchwork-Id: 293882 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oA15GY1q019448 for ; Mon, 1 Nov 2010 05:16:57 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 81FCAA02E1 for ; Sun, 31 Oct 2010 22:16:34 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id BF2329E911 for ; Sun, 31 Oct 2010 22:16:14 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 31 Oct 2010 22:16:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.58,271,1286175600"; d="scan'208";a="852831100" Received: from snb-linux.sh.intel.com ([10.239.13.102]) by fmsmga001.fm.intel.com with ESMTP; 31 Oct 2010 22:16:13 -0700 From: Zou Nan hai To: intel-gfx@lists.freedesktop.org Date: Mon, 1 Nov 2010 13:23:35 +0800 Message-Id: <1288589016-1439-1-git-send-email-nanhai.zou@intel.com> X-Mailer: git-send-email 1.7.1 Subject: [Intel-gfx] [PATCH 1/2] add BLT ring support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Mon, 01 Nov 2010 05:16:57 +0000 (UTC) diff --git a/src/i830_reg.h b/src/i830_reg.h index 4080896..93d03cf 100644 --- a/src/i830_reg.h +++ b/src/i830_reg.h @@ -32,6 +32,8 @@ /* Flush */ #define MI_FLUSH (0x04<<23) +#define MI_FLUSH_DW (0x26<<23) + #define MI_WRITE_DIRTY_STATE (1<<4) #define MI_END_SCENE (1<<3) #define MI_GLOBAL_SNAPSHOT_COUNT_RESET (1<<3) diff --git a/src/intel.h b/src/intel.h index b74a061..f3e5a39 100644 --- a/src/intel.h +++ b/src/intel.h @@ -276,6 +276,10 @@ typedef struct intel_screen_private { unsigned char *MMIOBase; int cpp; +#define RENDER_BATCH I915_EXEC_RENDER +#define BLT_BATCH I915_EXEC_BLT + unsigned int current_batch; + unsigned int bufferOffset; /* for I830SelectBuffer */ /* These are set in PreInit and never changed. */ diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c index e7ca69d..84d4515 100644 --- a/src/intel_batchbuffer.c +++ b/src/intel_batchbuffer.c @@ -147,14 +147,22 @@ void intel_batch_emit_flush(ScrnInfoPtr scrn) assert (!intel->in_batch_atomic); /* Big hammer, look to the pipelined flushes in future. */ - flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE; - if (INTEL_INFO(intel)->gen >= 40) - flags = 0; - - BEGIN_BATCH(1); - OUT_BATCH(MI_FLUSH | flags); - ADVANCE_BATCH(); - + if (intel->current_batch == BLT_BATCH) { + BEGIN_BATCH_BLT(4); + OUT_BATCH(MI_FLUSH_DW | 2); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + } else { + flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE; + if (INTEL_INFO(intel)->gen >= 40) + flags = 0; + + BEGIN_BATCH(1); + OUT_BATCH(MI_FLUSH | flags); + ADVANCE_BATCH(); + } intel_batch_do_flush(scrn); } @@ -190,9 +198,11 @@ void intel_batch_submit(ScrnInfoPtr scrn, int flush) } ret = dri_bo_subdata(intel->batch_bo, 0, intel->batch_used*4, intel->batch_ptr); - if (ret == 0) - ret = dri_bo_exec(intel->batch_bo, intel->batch_used*4, - NULL, 0, 0xffffffff); + if (ret == 0) + ret = drm_intel_bo_mrb_exec(intel->batch_bo, + intel->batch_used*4, + NULL, 0, 0xffffffff, intel->current_batch); + if (ret != 0) { if (ret == -EIO) { static int once; diff --git a/src/intel_batchbuffer.h b/src/intel_batchbuffer.h index bf7a5d9..5863561 100644 --- a/src/intel_batchbuffer.h +++ b/src/intel_batchbuffer.h @@ -63,7 +63,9 @@ static inline void intel_batch_start_atomic(ScrnInfoPtr scrn, unsigned int sz) intel_screen_private *intel = intel_get_screen_private(scrn); assert(!intel->in_batch_atomic); + intel_batch_require_space(scrn, intel, sz * 4); + intel->current_batch = RENDER_BATCH; \ intel->in_batch_atomic = TRUE; intel->batch_atomic_limit = intel->batch_used + sz; @@ -173,17 +175,23 @@ union intfloat { OUT_BATCH(tmp.ui); \ } while(0) -#define BEGIN_BATCH(n) \ +#define __BEGIN_BATCH(n,batch_idx) \ do { \ if (intel->batch_emitting != 0) \ FatalError("%s: BEGIN_BATCH called without closing " \ "ADVANCE_BATCH\n", __FUNCTION__); \ assert(!intel->in_batch_atomic); \ + if (intel->current_batch != batch_idx) \ + intel_batch_submit(scrn, FALSE); \ intel_batch_require_space(scrn, intel, (n) * 4); \ + intel->current_batch = batch_idx; \ intel->batch_emitting = (n); \ intel->batch_emit_start = intel->batch_used; \ } while (0) +#define BEGIN_BATCH(n) __BEGIN_BATCH(n,RENDER_BATCH) +#define BEGIN_BATCH_BLT(n) __BEGIN_BATCH(n,BLT_BATCH) + #define ADVANCE_BATCH() do { \ if (intel->batch_emitting == 0) \ FatalError("%s: ADVANCE_BATCH called with no matching " \