From patchwork Mon Nov 1 05:23:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zou, Nanhai" X-Patchwork-Id: 293892 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oA15H0OA019512 for ; Mon, 1 Nov 2010 05:17:20 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C3D3EA08A4 for ; Sun, 31 Oct 2010 22:17:00 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 5464B9E911 for ; Sun, 31 Oct 2010 22:16:15 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 31 Oct 2010 22:16:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.58,271,1286175600"; d="scan'208";a="852831107" Received: from snb-linux.sh.intel.com ([10.239.13.102]) by fmsmga001.fm.intel.com with ESMTP; 31 Oct 2010 22:16:14 -0700 From: Zou Nan hai To: intel-gfx@lists.freedesktop.org Date: Mon, 1 Nov 2010 13:23:36 +0800 Message-Id: <1288589016-1439-2-git-send-email-nanhai.zou@intel.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1288589016-1439-1-git-send-email-nanhai.zou@intel.com> References: <1288589016-1439-1-git-send-email-nanhai.zou@intel.com> Subject: [Intel-gfx] [PATCH 2/2] support BLT acceleration on gen6 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Mon, 01 Nov 2010 05:17:20 +0000 (UTC) diff --git a/src/intel_driver.c b/src/intel_driver.c index b16913b..160d08d 100644 --- a/src/intel_driver.c +++ b/src/intel_driver.c @@ -573,8 +573,6 @@ static Bool I830PreInit(ScrnInfoPtr scrn, int flags) } intel->use_shadow = FALSE; - if (IS_GEN6(intel)) - intel->use_shadow = TRUE; if (xf86IsOptionSet(intel->Options, OPTION_SHADOW)) { intel->use_shadow = diff --git a/src/intel_uxa.c b/src/intel_uxa.c index 23679bc..6605e20 100644 --- a/src/intel_uxa.c +++ b/src/intel_uxa.c @@ -207,16 +207,9 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap, } static Bool -i830_uxa_check_solid(DrawablePtr drawable, int alu, Pixel planemask) +intel_uxa_check_solid(DrawablePtr drawable, int alu, Pixel planemask) { ScrnInfoPtr scrn = xf86Screens[drawable->pScreen->myNum]; - intel_screen_private *intel = intel_get_screen_private(scrn); - - if (IS_GEN6(intel)) { - intel_debug_fallback(scrn, - "Sandybridge BLT engine not supported\n"); - return FALSE; - } if (!UXA_PM_IS_SOLID(drawable, planemask)) { intel_debug_fallback(scrn, "planemask is not solid\n"); @@ -239,7 +232,7 @@ i830_uxa_check_solid(DrawablePtr drawable, int alu, Pixel planemask) * Sets up hardware state for a series of solid fills. */ static Bool -i830_uxa_prepare_solid(PixmapPtr pixmap, int alu, Pixel planemask, Pixel fg) +intel_uxa_prepare_solid(PixmapPtr pixmap, int alu, Pixel planemask, Pixel fg) { ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); @@ -272,7 +265,7 @@ i830_uxa_prepare_solid(PixmapPtr pixmap, int alu, Pixel planemask, Pixel fg) return TRUE; } -static void i830_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2) +static void intel_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2) { ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); @@ -294,7 +287,10 @@ static void i830_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2) pitch = intel_pixmap_pitch(pixmap); { - BEGIN_BATCH(6); + if (IS_GEN6(intel)) + BEGIN_BATCH_BLT(6); + else + BEGIN_BATCH(6); cmd = XY_COLOR_BLT_CMD; @@ -322,7 +318,7 @@ static void i830_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2) ironlake_blt_workaround(scrn); } -static void i830_uxa_done_solid(PixmapPtr pixmap) +static void intel_uxa_done_solid(PixmapPtr pixmap) { ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum]; @@ -334,17 +330,10 @@ static void i830_uxa_done_solid(PixmapPtr pixmap) * - support planemask using FULL_BLT_CMD? */ static Bool -i830_uxa_check_copy(PixmapPtr source, PixmapPtr dest, +intel_uxa_check_copy(PixmapPtr source, PixmapPtr dest, int alu, Pixel planemask) { ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; - intel_screen_private *intel = intel_get_screen_private(scrn); - - if (IS_GEN6(intel)) { - intel_debug_fallback(scrn, - "Sandybridge BLT engine not supported\n"); - return FALSE; - } if (!UXA_PM_IS_SOLID(&source->drawable, planemask)) { intel_debug_fallback(scrn, "planemask is not solid"); @@ -373,7 +362,7 @@ i830_uxa_check_copy(PixmapPtr source, PixmapPtr dest, } static Bool -i830_uxa_prepare_copy(PixmapPtr source, PixmapPtr dest, int xdir, +intel_uxa_prepare_copy(PixmapPtr source, PixmapPtr dest, int xdir, int ydir, int alu, Pixel planemask) { ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; @@ -405,7 +394,7 @@ i830_uxa_prepare_copy(PixmapPtr source, PixmapPtr dest, int xdir, } static void -i830_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1, +intel_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1, int dst_y1, int w, int h) { ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; @@ -448,7 +437,10 @@ i830_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1, src_pitch = intel_pixmap_pitch(intel->render_source); { - BEGIN_BATCH(8); + if (IS_GEN6(intel)) + BEGIN_BATCH_BLT(8); + else + BEGIN_BATCH(8); cmd = XY_SRC_COPY_BLT_CMD; @@ -491,7 +483,7 @@ i830_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1, ironlake_blt_workaround(scrn); } -static void i830_uxa_done_copy(PixmapPtr dest) +static void intel_uxa_done_copy(PixmapPtr dest) { ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; @@ -1186,16 +1178,16 @@ Bool intel_uxa_init(ScreenPtr screen) intel->vertex_bo = NULL; /* Solid fill */ - intel->uxa_driver->check_solid = i830_uxa_check_solid; - intel->uxa_driver->prepare_solid = i830_uxa_prepare_solid; - intel->uxa_driver->solid = i830_uxa_solid; - intel->uxa_driver->done_solid = i830_uxa_done_solid; + intel->uxa_driver->check_solid = intel_uxa_check_solid; + intel->uxa_driver->prepare_solid = intel_uxa_prepare_solid; + intel->uxa_driver->solid = intel_uxa_solid; + intel->uxa_driver->done_solid = intel_uxa_done_solid; /* Copy */ - intel->uxa_driver->check_copy = i830_uxa_check_copy; - intel->uxa_driver->prepare_copy = i830_uxa_prepare_copy; - intel->uxa_driver->copy = i830_uxa_copy; - intel->uxa_driver->done_copy = i830_uxa_done_copy; + intel->uxa_driver->check_copy = intel_uxa_check_copy; + intel->uxa_driver->prepare_copy = intel_uxa_prepare_copy; + intel->uxa_driver->copy = intel_uxa_copy; + intel->uxa_driver->done_copy = intel_uxa_done_copy; /* Composite */ if (IS_GEN2(intel)) {