@@ -1274,6 +1274,30 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
intel_wait_for_pipe_off(dev_priv->dev, pipe);
}
+/* Check that the DSPADDR points to the right framebufffer for the pipe. */
+static void assert_fb_bound_to_plane(struct drm_i915_private *dev_priv,
+ enum pipe pipe, enum plane *plane)
+{
+ struct drm_crtc *crtc;
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+ u32 val, base, size;
+
+ crtc = intel_get_crtc_for_pipe(dev, pipe);
+ if (WARN(crtc->fb == NULL,
+ "no framebuffer attached to pipe %c\n",
+ pipe_name(pipe)))
+ return;
+
+ intel_fb = to_intel_framebuffer(crtc->fb);
+ base = intel_fb->obj->gtt_offset;
+ size = intel_fb->obj->base.size;
+
+ val = I915_READ(DSPADDR(plane));
+ WARN(val < offset || val >= base + size,
+ "mismatching framebuffer for plane %c attached to pipe %c\n",
+ plane_name(plane), pipe_name(pipe));
+}
+
/**
* intel_enable_plane - enable a display plane on a given pipe
* @dev_priv: i915 private structure
@@ -1290,6 +1314,7 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv,
/* If the pipe isn't enabled, we can't pump pixels and may hang */
assert_pipe_enabled(dev_priv, pipe);
+ assert_fb_bound_to_plane(dev_priv, pipe, plane);
reg = DSPCNTR(plane);
val = I915_READ(reg);
Knut Petersen reported a GPU hang when he left x11perf running overnight. The error state quite clearly indicates that plane A was enabled without being fully setup: PGTBL_ER: 0x00000010 Display A: Invalid GTT PTE Plane [0]: CNTR: c1000000 STRIDE: 00000c80 SIZE: 03ff04ff POS: 00000000 ADDR: 00000000 [GTT offset on his system being pinned for the ringbuffer.] This is a simple debugging patch to assert that this cannot be so! References: https://bugs.freedesktop.org/show_bug.cgi?id=36246 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> --- drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++++ 1 files changed, 25 insertions(+), 0 deletions(-)