diff mbox

drm/i915: load the LUT before pipe enable on ILK+

Message ID 1308173553-2797-1-git-send-email-jbarnes@virtuousgeek.org
State New, archived
Headers show

Commit Message

Jesse Barnes June 15, 2011, 9:32 p.m. UTC
Per the specs and to address
https://bugs.freedesktop.org/show_bug.cgi?id=36888.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

Comments

Jesse Barnes July 22, 2011, 7:54 p.m. UTC | #1
On Wed, 15 Jun 2011 23:32:33 +0200
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> Per the specs and to address
> https://bugs.freedesktop.org/show_bug.cgi?id=36888.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    8 ++++++--
>  1 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 81a9059..03ce9fa 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2699,14 +2699,18 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  		I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
>  	}
>  
> +	/*
> +	 * On ILK+ LUT must be loaded before the pipe is running but with
> +	 * clocks enabled
> +	 */
> +	intel_crtc_load_lut(crtc);
> +
>  	intel_enable_pipe(dev_priv, pipe, is_pch_port);
>  	intel_enable_plane(dev_priv, plane, pipe);
>  
>  	if (is_pch_port)
>  		ironlake_pch_enable(crtc);
>  
> -	intel_crtc_load_lut(crtc);
> -
>  	mutex_lock(&dev->struct_mutex);
>  	intel_update_fbc(dev);
>  	mutex_unlock(&dev->struct_mutex);

Keith, please pull this one in for 3.1.  Hardware will wedge if we try
to access the palette after pipe enable but before FDI or eDP training
completes, so we may as well just do it right before pipe enable.

Thanks,
Keith Packard July 22, 2011, 8:41 p.m. UTC | #2
On Fri, 22 Jul 2011 12:54:22 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> Keith, please pull this one in for 3.1.  Hardware will wedge if we try
> to access the palette after pipe enable but before FDI or eDP training
> completes, so we may as well just do it right before pipe enable.

I've stuck this on drm-intel-fixes, which is on top of 3.0 at this
point.
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 81a9059..03ce9fa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2699,14 +2699,18 @@  static void ironlake_crtc_enable(struct drm_crtc *crtc)
 		I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
 	}
 
+	/*
+	 * On ILK+ LUT must be loaded before the pipe is running but with
+	 * clocks enabled
+	 */
+	intel_crtc_load_lut(crtc);
+
 	intel_enable_pipe(dev_priv, pipe, is_pch_port);
 	intel_enable_plane(dev_priv, plane, pipe);
 
 	if (is_pch_port)
 		ironlake_pch_enable(crtc);
 
-	intel_crtc_load_lut(crtc);
-
 	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
 	mutex_unlock(&dev->struct_mutex);