From patchwork Mon Jun 20 01:14:06 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 895692 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p5K1FDj7032761 for ; Mon, 20 Jun 2011 01:15:33 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B79489E7EB for ; Sun, 19 Jun 2011 18:15:13 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from cloud01.chad-versace.us (184-106-247-128.static.cloud-ips.com [184.106.247.128]) by gabe.freedesktop.org (Postfix) with ESMTP id 53E8D9E787 for ; Sun, 19 Jun 2011 18:14:24 -0700 (PDT) Received: from localhost.localdomain (unknown [67.208.96.87]) by cloud01.chad-versace.us (Postfix) with ESMTPSA id 5A9791D4078; Mon, 20 Jun 2011 01:16:25 +0000 (UTC) From: Ben Widawsky To: mesa-dev@lists.freedesktop.org Date: Sun, 19 Jun 2011 18:14:06 -0700 Message-Id: <1308532451-7447-2-git-send-email-ben@bwidawsk.net> X-Mailer: git-send-email 1.7.5.2 In-Reply-To: <1308532451-7447-1-git-send-email-ben@bwidawsk.net> References: <1308532451-7447-1-git-send-email-ben@bwidawsk.net> Cc: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [Mesa-dev] [PATCH 1/6] i965: step message register allocation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 20 Jun 2011 01:15:33 +0000 (UTC) The system routine requires m0 be reserved. for saving off architectural state. Moved the allocation to start at 2 instead of 0. Signed-off-by: Ben Widawsky --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index b485787..d8957c5 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -1466,7 +1466,7 @@ fs_visitor::emit_dummy_fs() fs_inst *write; write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); - write->base_mrf = 0; + write->base_mrf = 2; } /* The register location here is relative to the start of the URB @@ -1627,7 +1627,7 @@ fs_visitor::emit_fb_writes() { this->current_annotation = "FB write header"; GLboolean header_present = GL_TRUE; - int nr = 0; + int nr = 2; int reg_width = c->dispatch_width / 8; if (intel->gen >= 6 && @@ -1637,7 +1637,7 @@ fs_visitor::emit_fb_writes() } if (header_present) { - /* m0, m1 header */ + /* m2, m3 header */ nr += 2; } @@ -1706,7 +1706,7 @@ fs_visitor::emit_fb_writes() fs_inst *inst = emit(FS_OPCODE_FB_WRITE); inst->target = target; - inst->base_mrf = 0; + inst->base_mrf = 2; inst->mlen = nr; if (target == c->key.nr_color_regions - 1) inst->eot = true; @@ -1724,7 +1724,7 @@ fs_visitor::emit_fb_writes() } fs_inst *inst = emit(FS_OPCODE_FB_WRITE); - inst->base_mrf = 0; + inst->base_mrf = 2; inst->mlen = nr; inst->eot = true; inst->header_present = header_present;