From patchwork Wed Jun 22 16:47:43 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Xiang, Haihao" X-Patchwork-Id: 904072 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p5M8p72J013659 for ; Wed, 22 Jun 2011 08:51:28 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 27C0A9E79E for ; Wed, 22 Jun 2011 01:51:07 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id DE0CFA01E1 for ; Wed, 22 Jun 2011 01:48:11 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 22 Jun 2011 01:48:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.65,405,1304319600"; d="scan'208";a="18180505" Received: from xhh-snb32.sh.intel.com (HELO localhost.localdomain) ([10.239.36.49]) by orsmga001.jf.intel.com with ESMTP; 22 Jun 2011 01:48:11 -0700 From: "Xiang, Haihao" To: intel-gfx@lists.freedesktop.org Date: Thu, 23 Jun 2011 00:47:43 +0800 Message-Id: <1308761267-13598-2-git-send-email-haihao.xiang@intel.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1308761267-13598-1-git-send-email-haihao.xiang@intel.com> References: <1308761267-13598-1-git-send-email-haihao.xiang@intel.com> Subject: [Intel-gfx] [PATCH 1/5] Xv: separate fragments from M4 macros X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 22 Jun 2011 08:51:29 +0000 (UTC) It is to prepare for Xv on Ivybridge. The difference from Sandybridge is that all message payload must be in GRF registers instead of MRF registers on Ivybridge. We will only redefine some M4 macros for Ivybridge Signed-off-by: Xiang, Haihao --- src/render_program/Makefile.am | 13 ++++- src/render_program/exa_wm_affine.g6i | 35 ++++++++++++ src/render_program/exa_wm_mask_affine.g6a | 8 +--- src/render_program/exa_wm_sample_planar.g4i | 64 +++++++++++++++++++++++ src/render_program/exa_wm_src_affine.g6a | 8 +--- src/render_program/exa_wm_src_sample_argb.g4a | 18 +------ src/render_program/exa_wm_src_sample_argb.g4i | 44 ++++++++++++++++ src/render_program/exa_wm_src_sample_planar.g4a | 36 +------------ src/render_program/exa_wm_write.g6a | 38 +------------- src/render_program/exa_wm_write.g6i | 61 +++++++++++++++++++++ 10 files changed, 219 insertions(+), 106 deletions(-) create mode 100644 src/render_program/exa_wm_affine.g6i create mode 100644 src/render_program/exa_wm_sample_planar.g4i create mode 100644 src/render_program/exa_wm_src_sample_argb.g4i create mode 100644 src/render_program/exa_wm_write.g6i diff --git a/src/render_program/Makefile.am b/src/render_program/Makefile.am index 1a19437..8e48d27 100644 --- a/src/render_program/Makefile.am +++ b/src/render_program/Makefile.am @@ -20,7 +20,9 @@ INTEL_G4A = \ INTEL_G4I = \ exa_wm.g4i \ exa_wm_affine.g4i \ - exa_wm_projective.g4i + exa_wm_projective.g4i \ + exa_wm_sample_planar.g4i \ + exa_wm_src_sample_argb.g4i INTEL_G4B = \ exa_sf.g4b \ @@ -61,6 +63,10 @@ INTEL_G4B_GEN5 = \ exa_wm_yuv_rgb.g4b.gen5 \ exa_wm_xy.g4b.gen5 +INTEL_G6I = \ + exa_wm_affine.g6i \ + exa_wm_write.g6i + INTEL_G6A = \ exa_wm_src_affine.g6a \ exa_wm_src_projective.g6a \ @@ -99,7 +105,8 @@ EXTRA_DIST = \ $(INTEL_G4B) \ $(INTEL_G4B_GEN5)\ $(INTEL_G6A) \ - $(INTEL_G6B) + $(INTEL_G6B) \ + $(INTEL_G6I) if HAVE_GEN4ASM @@ -111,7 +118,7 @@ SUFFIXES = .g4a .g4b .g6a .g6b m4 -I$(srcdir) -s $< > $*.g6m && intel-gen4asm -g 6 -o $@ $*.g6m && rm $*.g6m $(INTEL_G4B): $(INTEL_G4I) -$(INTEL_G6B): $(INTEL_G4I) +$(INTEL_G6B): $(INTEL_G4I) $(INTEL_G6I) BUILT_SOURCES= $(INTEL_G4B) $(INTEL_G6B) diff --git a/src/render_program/exa_wm_affine.g6i b/src/render_program/exa_wm_affine.g6i new file mode 100644 index 0000000..9ac21d5 --- /dev/null +++ b/src/render_program/exa_wm_affine.g6i @@ -0,0 +1,35 @@ +/* + * Copyright © 2010-2011 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +/* + * Fragment to compute src u/v values + */ + +/* U */ +pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */ +pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */ + +/* V */ +pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */ +pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */ diff --git a/src/render_program/exa_wm_mask_affine.g6a b/src/render_program/exa_wm_mask_affine.g6a index 2daf4e2..04ad2a2 100644 --- a/src/render_program/exa_wm_mask_affine.g6a +++ b/src/render_program/exa_wm_mask_affine.g6a @@ -38,10 +38,4 @@ define(`bh', `g4.0<8,8,1>F') define(`a0_a_x',`g8.0<0,1,0>F') define(`a0_a_y',`g8.16<0,1,0>F') -/* U */ -pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */ -pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */ - -/* V */ -pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */ -pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */ +include(`exa_wm_affine.g6i') diff --git a/src/render_program/exa_wm_sample_planar.g4i b/src/render_program/exa_wm_sample_planar.g4i new file mode 100644 index 0000000..5452420 --- /dev/null +++ b/src/render_program/exa_wm_sample_planar.g4i @@ -0,0 +1,64 @@ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Wang Zhenyu + * Keith Packard + */ + +/* Sample the src surface in planar format */ + +/* prepare sampler read back gX register, which would be written back to output */ + +/* use simd16 sampler, param 0 is u, param 1 is v. */ +/* 'payload' loading, assuming tex coord start from g4 */ + +/* load r */ +mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; + +/* src_msg will be copied with g0, as it contains send desc */ +/* emit sampler 'send' cmd */ + +/* sample Y */ +mov (8) src_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/ +send (16) src_msg_ind /* msg reg index */ + src_sample_g<1>UW /* readback */ + null + sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ + +/* sample U (Cr) */ +send (16) src_msg_ind /* msg reg index */ + src_sample_r<1>UW /* readback */ + null + sampler (3,0,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ + +/* sample V (Cb) */ +send (16) src_msg_ind /* msg reg index */ + src_sample_b<1>UW /* readback */ + null + sampler (5,0,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ diff --git a/src/render_program/exa_wm_src_affine.g6a b/src/render_program/exa_wm_src_affine.g6a index 08195a4..38623bf 100644 --- a/src/render_program/exa_wm_src_affine.g6a +++ b/src/render_program/exa_wm_src_affine.g6a @@ -38,10 +38,4 @@ define(`bh', `g4.0<8,8,1>F') define(`a0_a_x',`g6.0<0,1,0>F') define(`a0_a_y',`g6.16<0,1,0>F') -/* U */ -pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */ -pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */ - -/* V */ -pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */ -pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */ +include(`exa_wm_affine.g6i') diff --git a/src/render_program/exa_wm_src_sample_argb.g4a b/src/render_program/exa_wm_src_sample_argb.g4a index 384fe26..02119e3 100644 --- a/src/render_program/exa_wm_src_sample_argb.g4a +++ b/src/render_program/exa_wm_src_sample_argb.g4a @@ -29,20 +29,4 @@ include(`exa_wm.g4i') -/* prepare sampler read back gX register, which would be written back to output */ - -/* use simd16 sampler, param 0 is u, param 1 is v. */ -/* 'payload' loading, assuming tex coord start from g4 */ - -/* load argb */ -mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable }; -mov (8) src_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/ - -/* src_msg will be copied with g0, as it contains send desc */ -/* emit sampler 'send' cmd */ -send (16) src_msg_ind /* msg reg index */ - src_sample_base<1>UW /* readback */ - null - sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) - /* here(src->dst) we should use src_sampler and src_surface */ - mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */ +include(`exa_wm_src_sample_argb.g4i') diff --git a/src/render_program/exa_wm_src_sample_argb.g4i b/src/render_program/exa_wm_src_sample_argb.g4i new file mode 100644 index 0000000..62d5afc --- /dev/null +++ b/src/render_program/exa_wm_src_sample_argb.g4i @@ -0,0 +1,44 @@ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Wang Zhenyu + * Keith Packard + */ + +/* prepare sampler read back gX register, which would be written back to output */ + +/* use simd16 sampler, param 0 is u, param 1 is v. */ +/* 'payload' loading, assuming tex coord start from g4 */ + +/* load argb */ +mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable }; +mov (8) src_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/ + +/* src_msg will be copied with g0, as it contains send desc */ +/* emit sampler 'send' cmd */ +send (16) src_msg_ind /* msg reg index */ + src_sample_base<1>UW /* readback */ + null + sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */ diff --git a/src/render_program/exa_wm_src_sample_planar.g4a b/src/render_program/exa_wm_src_sample_planar.g4a index 5f5520b..59678f5 100644 --- a/src/render_program/exa_wm_src_sample_planar.g4a +++ b/src/render_program/exa_wm_src_sample_planar.g4a @@ -29,38 +29,4 @@ include(`exa_wm.g4i') -/* prepare sampler read back gX register, which would be written back to output */ - -/* use simd16 sampler, param 0 is u, param 1 is v. */ -/* 'payload' loading, assuming tex coord start from g4 */ - -/* load r */ -mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; - -/* src_msg will be copied with g0, as it contains send desc */ -/* emit sampler 'send' cmd */ - -/* sample Y */ -mov (8) src_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/ -send (16) src_msg_ind /* msg reg index */ - src_sample_g<1>UW /* readback */ - null - sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) - /* here(src->dst) we should use src_sampler and src_surface */ - mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ - -/* sample U (Cr) */ -send (16) src_msg_ind /* msg reg index */ - src_sample_r<1>UW /* readback */ - null - sampler (3,0,F) /* sampler message description, (binding_table,sampler_index,datatype) - /* here(src->dst) we should use src_sampler and src_surface */ - mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ - -/* sample V (Cb) */ -send (16) src_msg_ind /* msg reg index */ - src_sample_b<1>UW /* readback */ - null - sampler (5,0,F) /* sampler message description, (binding_table,sampler_index,datatype) - /* here(src->dst) we should use src_sampler and src_surface */ - mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ +include(`exa_wm_sample_planar.g4i') diff --git a/src/render_program/exa_wm_write.g6a b/src/render_program/exa_wm_write.g6a index c0f3cc1..ed976b5 100644 --- a/src/render_program/exa_wm_write.g6a +++ b/src/render_program/exa_wm_write.g6a @@ -38,40 +38,4 @@ define(`slot_a_00', `m8') define(`slot_a_01', `m9') define(`data_port_msg_2_ind', `2') -mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 }; -mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 }; - -mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 }; -mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 }; - -mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 }; -mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 }; - -mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 }; -mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 }; - -/* write */ -send (16) - data_port_msg_2_ind - acc0<1>UW - null - write ( - 0, /* binding_table */ - 16, /* pixel scordboard clear, msg type simd16 single source */ - 12, /* render target write */ - 0, /* no write commit message */ - 0 /* headerless render target write */ - ) - mlen 8 - rlen 0 - { align1 EOT }; - -nop; -nop; -nop; -nop; -nop; -nop; -nop; -nop; - +include(`exa_wm_write.g6i') diff --git a/src/render_program/exa_wm_write.g6i b/src/render_program/exa_wm_write.g6i new file mode 100644 index 0000000..7be1db2 --- /dev/null +++ b/src/render_program/exa_wm_write.g6i @@ -0,0 +1,61 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 }; +mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 }; + +mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 }; +mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 }; + +mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 }; +mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 }; + +mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 }; +mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 }; + +/* write */ +send (16) + data_port_msg_2_ind + acc0<1>UW + null + write ( + 0, /* binding_table */ + 16, /* pixel scordboard clear, msg type simd16 single source */ + 12, /* render target write */ + 0, /* no write commit message */ + 0 /* headerless render target write */ + ) + mlen 8 + rlen 0 + { align1 EOT }; + +nop; +nop; +nop; +nop; +nop; +nop; +nop; +nop; +