diff mbox

[2/5] Xv: New shaders for Xv on Ivybridge

Message ID 1308761267-13598-3-git-send-email-haihao.xiang@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Xiang, Haihao June 22, 2011, 4:47 p.m. UTC
Redefine some M4 macros, also update the check for
intel-gen4asm to support Ivybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
---
 configure.ac                                    |    2 +-
 src/render_program/Makefile.am                  |   27 +++++++++++++--
 src/render_program/exa_wm_src_affine.g7a        |   41 +++++++++++++++++++++++
 src/render_program/exa_wm_src_affine.g7b        |    4 ++
 src/render_program/exa_wm_src_sample_argb.g7a   |   38 +++++++++++++++++++++
 src/render_program/exa_wm_src_sample_argb.g7b   |    3 ++
 src/render_program/exa_wm_src_sample_planar.g7a |   38 +++++++++++++++++++++
 src/render_program/exa_wm_src_sample_planar.g7b |    5 +++
 src/render_program/exa_wm_write.g7a             |   41 +++++++++++++++++++++++
 src/render_program/exa_wm_write.g7b             |   17 +++++++++
 src/render_program/exa_wm_yuv_rgb.g7a           |    1 +
 src/render_program/exa_wm_yuv_rgb.g7b           |   12 +++++++
 12 files changed, 225 insertions(+), 4 deletions(-)
 create mode 100644 src/render_program/exa_wm_src_affine.g7a
 create mode 100644 src/render_program/exa_wm_src_affine.g7b
 create mode 100644 src/render_program/exa_wm_src_sample_argb.g7a
 create mode 100644 src/render_program/exa_wm_src_sample_argb.g7b
 create mode 100644 src/render_program/exa_wm_src_sample_planar.g7a
 create mode 100644 src/render_program/exa_wm_src_sample_planar.g7b
 create mode 100644 src/render_program/exa_wm_write.g7a
 create mode 100644 src/render_program/exa_wm_write.g7b
 create mode 120000 src/render_program/exa_wm_yuv_rgb.g7a
 create mode 100644 src/render_program/exa_wm_yuv_rgb.g7b
diff mbox

Patch

diff --git a/configure.ac b/configure.ac
index 7bde768..e14bad0 100644
--- a/configure.ac
+++ b/configure.ac
@@ -61,7 +61,7 @@  m4_ifndef([XORG_DRIVER_CHECK_EXT],
 LT_PREREQ([2.2])
 LT_INIT([disable-static])
 
-PKG_CHECK_MODULES(GEN4ASM, [intel-gen4asm >= 1.1], [gen4asm=yes], [gen4asm=no])
+PKG_CHECK_MODULES(GEN4ASM, [intel-gen4asm >= 1.2], [gen4asm=yes], [gen4asm=no])
 AM_CONDITIONAL(HAVE_GEN4ASM, test x$gen4asm = xyes)
 
 PKG_CHECK_MODULES(UDEV, [libudev], [udev=yes], [udev=no])
diff --git a/src/render_program/Makefile.am b/src/render_program/Makefile.am
index 8e48d27..d7045fa 100644
--- a/src/render_program/Makefile.am
+++ b/src/render_program/Makefile.am
@@ -99,6 +99,20 @@  INTEL_G6B =				\
 	exa_wm_write.g6b 		\
 	exa_wm_yuv_rgb.g6b
 
+INTEL_G7A =				\
+	exa_wm_src_affine.g7a 		\
+	exa_wm_src_sample_argb.g7a 	\
+	exa_wm_src_sample_planar.g7a 	\
+	exa_wm_write.g7a 		\
+	exa_wm_yuv_rgb.g7a
+
+INTEL_G7B =				\
+	exa_wm_src_affine.g7b 		\
+	exa_wm_src_sample_argb.g7b 	\
+	exa_wm_src_sample_planar.g7b 	\
+	exa_wm_write.g7b 		\
+	exa_wm_yuv_rgb.g7b
+
 EXTRA_DIST = 		\
 	$(INTEL_G4A)	\
 	$(INTEL_G4I)	\
@@ -106,23 +120,30 @@  EXTRA_DIST = 		\
 	$(INTEL_G4B_GEN5)\
 	$(INTEL_G6A)	\
 	$(INTEL_G6B)	\
-	$(INTEL_G6I)
+	$(INTEL_G6I)	\
+	$(INTEL_G7A)	\
+	$(INTEL_G7B)
 
 if HAVE_GEN4ASM
 
-SUFFIXES = .g4a .g4b .g6a .g6b
+SUFFIXES = .g4a .g4b .g6a .g6b .g7a .g7b
 .g4a.g4b:
 	m4 -I$(srcdir) -s $< > $*.g4m && intel-gen4asm -o $@ $*.g4m && intel-gen4asm -g 5 -o $@.gen5 $*.g4m && rm $*.g4m
 
 .g6a.g6b:
 	m4 -I$(srcdir) -s $< > $*.g6m && intel-gen4asm -g 6 -o $@ $*.g6m && rm $*.g6m
 
+.g7a.g7b:
+	m4 -I$(srcdir) -s $< > $*.g7m && intel-gen4asm -g 7 -o $@ $*.g7m && rm $*.g7m
+
 $(INTEL_G4B): $(INTEL_G4I)
 $(INTEL_G6B): $(INTEL_G4I) $(INTEL_G6I)
+$(INTEL_G7B): $(INTEL_G4I) $(INTEL_G6I)
 
-BUILT_SOURCES= $(INTEL_G4B) $(INTEL_G6B)
+BUILT_SOURCES= $(INTEL_G4B) $(INTEL_G6B) $(INTEL_G7B)
 
 clean-local:
 	-rm -f $(INTEL_G4B) $(INTEL_G4B_GEN5)
 	-rm -f $(INTEL_G6B)
+	-rm -f $(INTEL_G7B)
 endif
diff --git a/src/render_program/exa_wm_src_affine.g7a b/src/render_program/exa_wm_src_affine.g7a
new file mode 100644
index 0000000..cf24b2f
--- /dev/null
+++ b/src/render_program/exa_wm_src_affine.g7a
@@ -0,0 +1,41 @@ 
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+/*
+ * Fragment to compute src u/v values
+ */
+include(`exa_wm.g4i')
+
+define(`ul',    `g66')
+define(`uh',    `g67')
+define(`vl',    `g68')
+define(`vh',    `g69')
+
+define(`bl',    `g2.0<8,8,1>F')
+define(`bh',    `g4.0<8,8,1>F')
+
+define(`a0_a_x',`g6.0<0,1,0>F')
+define(`a0_a_y',`g6.16<0,1,0>F')
+
+include(`exa_wm_affine.g6i')
diff --git a/src/render_program/exa_wm_src_affine.g7b b/src/render_program/exa_wm_src_affine.g7b
new file mode 100644
index 0000000..f545fba
--- /dev/null
+++ b/src/render_program/exa_wm_src_affine.g7b
@@ -0,0 +1,4 @@ 
+   { 0x0060005a, 0x284077bd, 0x000000c0, 0x008d0040 },
+   { 0x0060005a, 0x286077bd, 0x000000c0, 0x008d0080 },
+   { 0x0060005a, 0x288077bd, 0x000000d0, 0x008d0040 },
+   { 0x0060005a, 0x28a077bd, 0x000000d0, 0x008d0080 },
diff --git a/src/render_program/exa_wm_src_sample_argb.g7a b/src/render_program/exa_wm_src_sample_argb.g7a
new file mode 100644
index 0000000..69f5ebc
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_argb.g7a
@@ -0,0 +1,38 @@ 
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Wang Zhenyu <zhenyu.z.wang@intel.com>
+ *    Keith Packard <keithp@keithp.com>
+ */
+
+/* Sample the src surface */
+
+include(`exa_wm.g4i')
+
+undefine(`src_msg')
+undefine(`src_msg_ind')
+
+define(`src_msg',       `g65')
+define(`src_msg_ind',   `65')
+
+include(`exa_wm_src_sample_argb.g4i')
diff --git a/src/render_program/exa_wm_src_sample_argb.g7b b/src/render_program/exa_wm_src_sample_argb.g7b
new file mode 100644
index 0000000..a282cf8
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_argb.g7b
@@ -0,0 +1,3 @@ 
+   { 0x00000201, 0x20080061, 0x00000000, 0x00000000 },
+   { 0x00600001, 0x28200021, 0x008d0000, 0x00000000 },
+   { 0x02800031, 0x21c01ca9, 0x00000820, 0x0a8c0001 },
diff --git a/src/render_program/exa_wm_src_sample_planar.g7a b/src/render_program/exa_wm_src_sample_planar.g7a
new file mode 100644
index 0000000..53b1211
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_planar.g7a
@@ -0,0 +1,38 @@ 
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Wang Zhenyu <zhenyu.z.wang@intel.com>
+ *    Keith Packard <keithp@keithp.com>
+ */
+
+/* Sample the src surface in planar format */
+
+include(`exa_wm.g4i')
+
+undefine(`src_msg')
+undefine(`src_msg_ind')
+
+define(`src_msg',       `g65')
+define(`src_msg_ind',   `65')
+
+include(`exa_wm_sample_planar.g4i')
diff --git a/src/render_program/exa_wm_src_sample_planar.g7b b/src/render_program/exa_wm_src_sample_planar.g7b
new file mode 100644
index 0000000..ddd6f36
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_planar.g7b
@@ -0,0 +1,5 @@ 
+   { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 },
+   { 0x00600001, 0x28200021, 0x008d0000, 0x00000000 },
+   { 0x02800031, 0x22001ca9, 0x00000820, 0x0a2c0001 },
+   { 0x02800031, 0x21c01ca9, 0x00000820, 0x0a2c0003 },
+   { 0x02800031, 0x22401ca9, 0x00000820, 0x0a2c0005 },
diff --git a/src/render_program/exa_wm_write.g7a b/src/render_program/exa_wm_write.g7a
new file mode 100644
index 0000000..d21f9b4
--- /dev/null
+++ b/src/render_program/exa_wm_write.g7a
@@ -0,0 +1,41 @@ 
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+include(`exa_wm.g4i')
+
+/*
+ * Prepare data in g66-g67 for Red channel, g68-g69 for Green channel,
+ * g70-g71 for Blue and g72-g73 for Alpha channel
+ */
+define(`slot_r_00',     `g66')
+define(`slot_r_01',     `g67')
+define(`slot_g_00',     `g68')
+define(`slot_g_01',     `g69')
+define(`slot_b_00',     `g70')
+define(`slot_b_01',     `g71')
+define(`slot_a_00',     `g72')
+define(`slot_a_01',     `g73')
+define(`data_port_msg_2_ind',	`66')
+
+include(`exa_wm_write.g6i')
diff --git a/src/render_program/exa_wm_write.g7b b/src/render_program/exa_wm_write.g7b
new file mode 100644
index 0000000..f31af51
--- /dev/null
+++ b/src/render_program/exa_wm_write.g7b
@@ -0,0 +1,17 @@ 
+   { 0x00600001, 0x284003bd, 0x008d01c0, 0x00000000 },
+   { 0x00600001, 0x286003bd, 0x008d01e0, 0x00000000 },
+   { 0x00600001, 0x288003bd, 0x008d0200, 0x00000000 },
+   { 0x00600001, 0x28a003bd, 0x008d0220, 0x00000000 },
+   { 0x00600001, 0x28c003bd, 0x008d0240, 0x00000000 },
+   { 0x00600001, 0x28e003bd, 0x008d0260, 0x00000000 },
+   { 0x00600001, 0x290003bd, 0x008d0280, 0x00000000 },
+   { 0x00600001, 0x292003bd, 0x008d02a0, 0x00000000 },
+   { 0x05800031, 0x24001ca8, 0x00000840, 0x90031000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+   { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/render_program/exa_wm_yuv_rgb.g7a b/src/render_program/exa_wm_yuv_rgb.g7a
new file mode 120000
index 0000000..d34d246
--- /dev/null
+++ b/src/render_program/exa_wm_yuv_rgb.g7a
@@ -0,0 +1 @@ 
+exa_wm_yuv_rgb.g4a
\ No newline at end of file
diff --git a/src/render_program/exa_wm_yuv_rgb.g7b b/src/render_program/exa_wm_yuv_rgb.g7b
new file mode 100644
index 0000000..01ec5e5
--- /dev/null
+++ b/src/render_program/exa_wm_yuv_rgb.g7b
@@ -0,0 +1,12 @@ 
+   { 0x00800040, 0x23007fbd, 0x008d0200, 0xbd808081 },
+   { 0x00800041, 0x23007fbd, 0x008d0300, 0x3f94fdf4 },
+   { 0x00800040, 0x22c07fbd, 0x008d01c0, 0xbf008084 },
+   { 0x00800040, 0x23407fbd, 0x008d0240, 0xbf008084 },
+   { 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 },
+   { 0x80800048, 0x21c07fbd, 0x008d02c0, 0x3fcc49ba },
+   { 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 },
+   { 0x00800048, 0x24007fbc, 0x008d02c0, 0xbf5020c5 },
+   { 0x80800048, 0x22007fbd, 0x008d0340, 0xbec8b439 },
+   { 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 },
+   { 0x80800048, 0x22407fbd, 0x008d0340, 0x40011687 },
+   { 0x00800001, 0x228003fd, 0x00000000, 0x3f800000 },