diff mbox

[5/5] Xv: set up pipeline for Xv on Ivybridge

Message ID 1308761267-13598-6-git-send-email-haihao.xiang@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Xiang, Haihao June 22, 2011, 4:47 p.m. UTC 
The configuration is same as that on Sandybridge, but
many state commands are changed

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
---
 src/i965_reg.h   |  132 ++++++++++++++++
 src/i965_video.c |  446 +++++++++++++++++++++++++++++++++++++++++++++++++++---
 2 files changed, 554 insertions(+), 24 deletions(-)

Comments

Owain Ainsworth June 24, 2011, 5:03 a.m. UTC | #1 
On Thu, Jun 23, 2011 at 12:47:47AM +0800, Xiang, Haihao wrote:
> The configuration is same as that on Sandybridge, but
> many state commands are changed
> 
> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
> ---
>  src/i965_reg.h   |  132 ++++++++++++++++
>  src/i965_video.c |  446 +++++++++++++++++++++++++++++++++++++++++++++++++++---
>  2 files changed, 554 insertions(+), 24 deletions(-)
> 
> diff --git a/src/i965_reg.h b/src/i965_reg.h
> index df41fba..ab6c020 100644
> --- a/src/i965_reg.h
> +++ b/src/i965_reg.h
> --- a/src/i965_video.c
> +++ b/src/i965_video.c
> @@ -1445,6 +1445,7 @@ gen6_create_blend_state(ScrnInfoPtr scrn)
>  
>  	blend_state->blend1.logic_op_enable = 1;
>  	blend_state->blend1.logic_op_func = 0xc;
> +	blend_state->blend1.pre_blend_clamp_enable = 1;
>  
>  	drm_intel_bo_unmap(blend_bo);
>  	return blend_bo;

Can you please explain why this chunk is added for all gen6 and above?

-0-
Xiang, Haihao June 24, 2011, 5:27 a.m. UTC | #2 
On Fri, 2011-06-24 at 13:03 +0800, Owain Ainsworth wrote:
> On Thu, Jun 23, 2011 at 12:47:47AM +0800, Xiang, Haihao wrote:
> > The configuration is same as that on Sandybridge, but
> > many state commands are changed
> > 
> > Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
> > ---
> >  src/i965_reg.h   |  132 ++++++++++++++++
> >  src/i965_video.c |  446 +++++++++++++++++++++++++++++++++++++++++++++++++++---
> >  2 files changed, 554 insertions(+), 24 deletions(-)
> > 
> > diff --git a/src/i965_reg.h b/src/i965_reg.h
> > index df41fba..ab6c020 100644
> > --- a/src/i965_reg.h
> > +++ b/src/i965_reg.h
> > --- a/src/i965_video.c
> > +++ b/src/i965_video.c
> > @@ -1445,6 +1445,7 @@ gen6_create_blend_state(ScrnInfoPtr scrn)
> >  
> >  	blend_state->blend1.logic_op_enable = 1;
> >  	blend_state->blend1.logic_op_func = 0xc;
> > +	blend_state->blend1.pre_blend_clamp_enable = 1;
> >  
> >  	drm_intel_bo_unmap(blend_bo);
> >  	return blend_bo;
> 
> Can you please explain why this chunk is added for all gen6 and above?
Sandybridge and Ivybridge have the same requirement about Pre-Blend
Color Clamp Enable. The document says it must be enabled if the format
of the render target is UNORM, and the DDX driver uses XXX_UNORM format
for Xv.
diff mbox

Patch

diff --git a/src/i965_reg.h b/src/i965_reg.h
index df41fba..ab6c020 100644
--- a/src/i965_reg.h
+++ b/src/i965_reg.h
@@ -136,6 +136,138 @@ 
 # define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_4			(2 << 1)
 # define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_8			(3 << 1)
 
+/* on GEN7+ */
+/* _3DSTATE_VERTEX_BUFFERS on GEN7*/
+/* DW1 */
+#define GEN7_VB0_ADDRESS_MODIFYENABLE   (1 << 14)
+
+/* _3DPRIMITIVE on GEN7 */
+/* DW1 */
+# define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL     (0 << 8)
+# define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM         (1 << 8)
+
+/* 3DSTATE_WM on GEN7 */
+/* DW1 */
+# define GEN7_WM_STATISTICS_ENABLE                              (1 << 31)
+# define GEN7_WM_DEPTH_CLEAR                                    (1 << 30)
+# define GEN7_WM_DISPATCH_ENABLE                                (1 << 29)
+# define GEN6_WM_DEPTH_RESOLVE                                  (1 << 28)
+# define GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE                     (1 << 27)
+# define GEN7_WM_KILL_ENABLE                                    (1 << 25)
+# define GEN7_WM_PSCDEPTH_OFF                                   (0 << 23)
+# define GEN7_WM_PSCDEPTH_ON                                    (1 << 23)
+# define GEN7_WM_PSCDEPTH_ON_GE                                 (2 << 23)
+# define GEN7_WM_PSCDEPTH_ON_LE                                 (3 << 23)
+# define GEN7_WM_USES_SOURCE_DEPTH                              (1 << 20)
+# define GEN7_WM_USES_SOURCE_W                                  (1 << 19)
+# define GEN7_WM_POSITION_ZW_PIXEL                              (0 << 17)
+# define GEN7_WM_POSITION_ZW_CENTROID                           (2 << 17)
+# define GEN7_WM_POSITION_ZW_SAMPLE                             (3 << 17)
+# define GEN7_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC              (1 << 16)
+# define GEN7_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC            (1 << 15)
+# define GEN7_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC               (1 << 14)
+# define GEN7_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC                 (1 << 13)
+# define GEN7_WM_PERSPECTIVE_CENTROID_BARYCENTRIC               (1 << 12)
+# define GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC                  (1 << 11)
+# define GEN7_WM_USES_INPUT_COVERAGE_MASK                       (1 << 10)
+# define GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5                      (0 << 8)
+# define GEN7_WM_LINE_END_CAP_AA_WIDTH_1_0                      (1 << 8)
+# define GEN7_WM_LINE_END_CAP_AA_WIDTH_2_0                      (2 << 8)
+# define GEN7_WM_LINE_END_CAP_AA_WIDTH_4_0                      (3 << 8)
+# define GEN7_WM_LINE_AA_WIDTH_0_5                              (0 << 6)
+# define GEN7_WM_LINE_AA_WIDTH_1_0                              (1 << 6)
+# define GEN7_WM_LINE_AA_WIDTH_2_0                              (2 << 6)
+# define GEN7_WM_LINE_AA_WIDTH_4_0                              (3 << 6)
+# define GEN7_WM_POLYGON_STIPPLE_ENABLE                         (1 << 4)
+# define GEN7_WM_LINE_STIPPLE_ENABLE                            (1 << 3)
+# define GEN7_WM_POINT_RASTRULE_UPPER_RIGHT                     (1 << 2)
+# define GEN7_WM_MSRAST_OFF_PIXEL                               (0 << 0)
+# define GEN7_WM_MSRAST_OFF_PATTERN                             (1 << 0)
+# define GEN7_WM_MSRAST_ON_PIXEL                                (2 << 0)
+# define GEN7_WM_MSRAST_ON_PATTERN                              (3 << 0)
+/* DW2 */
+# define GEN7_WM_MSDISPMODE_PERPIXEL                            (1 << 31)
+
+#define GEN7_3DSTATE_CLEAR_PARAMS               BRW_3D(3, 0, 0x04)
+#define GEN7_3DSTATE_DEPTH_BUFFER               BRW_3D(3, 0, 0x05)
+
+#define GEN7_3DSTATE_CONSTANT_HS                BRW_3D(3, 0, 0x19)
+#define GEN7_3DSTATE_CONSTANT_DS                BRW_3D(3, 0, 0x1a)
+
+#define GEN7_3DSTATE_HS                         BRW_3D(3, 0, 0x1b)
+#define GEN7_3DSTATE_TE                         BRW_3D(3, 0, 0x1c)
+#define GEN7_3DSTATE_DS                         BRW_3D(3, 0, 0x1d)
+#define GEN7_3DSTATE_STREAMOUT                  BRW_3D(3, 0, 0x1e)
+#define GEN7_3DSTATE_SBE                        BRW_3D(3, 0, 0x1f)
+
+/* DW1 */
+# define GEN7_SBE_SWIZZLE_CONTROL_MODE          (1 << 28)
+# define GEN7_SBE_NUM_OUTPUTS_SHIFT             22
+# define GEN7_SBE_SWIZZLE_ENABLE                (1 << 21)
+# define GEN7_SBE_POINT_SPRITE_LOWERLEFT        (1 << 20)
+# define GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT   11
+# define GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT   4
+
+#define GEN7_3DSTATE_PS                                 BRW_3D(3, 0, 0x20)
+/* DW1: kernel pointer */
+/* DW2 */
+# define GEN7_PS_SPF_MODE                               (1 << 31)
+# define GEN7_PS_VECTOR_MASK_ENABLE                     (1 << 30)
+# define GEN7_PS_SAMPLER_COUNT_SHIFT                    27
+# define GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT        18
+# define GEN7_PS_FLOATING_POINT_MODE_IEEE_754           (0 << 16)
+# define GEN7_PS_FLOATING_POINT_MODE_ALT                (1 << 16)
+/* DW3: scratch space */
+/* DW4 */
+# define GEN7_PS_MAX_THREADS_SHIFT                      23
+# define GEN7_PS_PUSH_CONSTANT_ENABLE                   (1 << 11)
+# define GEN7_PS_ATTRIBUTE_ENABLE                       (1 << 10)
+# define GEN7_PS_OMASK_TO_RENDER_TARGET                 (1 << 9)
+# define GEN7_PS_DUAL_SOURCE_BLEND_ENABLE               (1 << 7)
+# define GEN7_PS_POSOFFSET_NONE                         (0 << 3)
+# define GEN7_PS_POSOFFSET_CENTROID                     (2 << 3)
+# define GEN7_PS_POSOFFSET_SAMPLE                       (3 << 3)
+# define GEN7_PS_32_DISPATCH_ENABLE                     (1 << 2)
+# define GEN7_PS_16_DISPATCH_ENABLE                     (1 << 1)
+# define GEN7_PS_8_DISPATCH_ENABLE                      (1 << 0)
+/* DW5 */
+# define GEN7_PS_DISPATCH_START_GRF_SHIFT_0             16
+# define GEN7_PS_DISPATCH_START_GRF_SHIFT_1             8
+# define GEN7_PS_DISPATCH_START_GRF_SHIFT_2             0
+/* DW6: kernel 1 pointer */
+/* DW7: kernel 2 pointer */
+
+#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL      BRW_3D(3, 0, 0x21)
+#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC         BRW_3D(3, 0, 0x23)
+
+#define GEN7_3DSTATE_BLEND_STATE_POINTERS               BRW_3D(3, 0, 0x24)
+#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS       BRW_3D(3, 0, 0x25)
+
+#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS          BRW_3D(3, 0, 0x26)
+#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS          BRW_3D(3, 0, 0x27)
+#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS          BRW_3D(3, 0, 0x28)
+#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS          BRW_3D(3, 0, 0x29)
+#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS          BRW_3D(3, 0, 0x2a)
+
+#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS          BRW_3D(3, 0, 0x2b)
+#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS          BRW_3D(3, 0, 0x2e)
+#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS          BRW_3D(3, 0, 0x2f)
+
+#define GEN7_3DSTATE_URB_VS                             BRW_3D(3, 0, 0x30)
+#define GEN7_3DSTATE_URB_HS                             BRW_3D(3, 0, 0x31)
+#define GEN7_3DSTATE_URB_DS                             BRW_3D(3, 0, 0x32)
+#define GEN7_3DSTATE_URB_GS                             BRW_3D(3, 0, 0x33)
+/* DW1 */
+# define GEN7_URB_ENTRY_NUMBER_SHIFT            0
+# define GEN7_URB_ENTRY_SIZE_SHIFT              16
+# define GEN7_URB_STARTING_ADDRESS_SHIFT        25
+
+#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS             BRW_3D(3, 1, 0x12)
+#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS             BRW_3D(3, 1, 0x16)
+/* DW1 */
+# define GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT 16
+
+
 #define PIPELINE_SELECT_3D		0
 #define PIPELINE_SELECT_MEDIA		1
 
diff --git a/src/i965_video.c b/src/i965_video.c
index 84230a1..1054914 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -1445,6 +1445,7 @@  gen6_create_blend_state(ScrnInfoPtr scrn)
 
 	blend_state->blend1.logic_op_enable = 1;
 	blend_state->blend1.logic_op_func = 0xc;
+	blend_state->blend1.pre_blend_clamp_enable = 1;
 
 	drm_intel_bo_unmap(blend_bo);
 	return blend_bo;
@@ -1811,8 +1812,44 @@  gen6_upload_vertex_element_state(ScrnInfoPtr scrn)
 		(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
 }
 
+static void 
+gen6_upload_vertex_buffer(ScrnInfoPtr scrn, drm_intel_bo *vertex_bo, uint32_t end_address_offset)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	/* Set up the pointer to our vertex buffer */
+	OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | (5 - 2));
+	/* four 32-bit floats per vertex */
+	OUT_BATCH((0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
+		GEN6_VB0_VERTEXDATA | 
+		((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
+	OUT_RELOC(vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
+	OUT_RELOC(vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, end_address_offset);
+	OUT_BATCH(0);	/* reserved */
+}
+
 static void
-gen6_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo *surface_state_binding_table_bo, int n_src_surf, PixmapPtr pixmap)
+gen6_upload_primitive(ScrnInfoPtr scrn)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	OUT_BATCH(BRW_3DPRIMITIVE | 
+		BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL | 
+		(_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) | 
+		(0 << 9) | /* Internal Vertex Count */
+		(6 - 2));
+	OUT_BATCH(3);	/* vertex count per instance */
+	OUT_BATCH(0);	/* start vertex offset */
+	OUT_BATCH(1);	/* single instance */
+	OUT_BATCH(0);	/* start instance location */
+	OUT_BATCH(0);	/* index buffer offset, ignored */
+}
+
+static void
+gen6_emit_video_setup(ScrnInfoPtr scrn,
+		drm_intel_bo *surface_state_binding_table_bo, int n_src_surf,
+		PixmapPtr pixmap,
+		drm_intel_bo *vertex_bo, uint32_t end_address_offset)
 {
 	intel_screen_private *intel = intel_get_screen_private(scrn);
 
@@ -1835,6 +1872,382 @@  gen6_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo *surface_state_binding_tabl
 	gen6_upload_depth_buffer_state(scrn);
 	gen6_upload_drawing_rectangle(scrn, pixmap);
 	gen6_upload_vertex_element_state(scrn);
+	gen6_upload_vertex_buffer(scrn, vertex_bo, end_address_offset);
+	gen6_upload_primitive(scrn);
+}
+
+static void
+gen7_upload_invarient_states(ScrnInfoPtr scrn)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
+	OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH |
+		BRW_PIPE_CONTROL_WC_FLUSH |
+		BRW_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+		BRW_PIPE_CONTROL_NOWRITE);
+	OUT_BATCH(0); /* write address */
+	OUT_BATCH(0); /* write data */
+
+	OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+
+	OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (4 - 2));
+	OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
+		GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
+	OUT_BATCH(1);
+
+	/* Set system instruction pointer */
+	OUT_BATCH(BRW_STATE_SIP | 0);
+	OUT_BATCH(0);
+}
+
+static void
+gen7_upload_viewport_state_pointers(ScrnInfoPtr scrn)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
+	OUT_RELOC(intel->video.gen4_cc_vp_bo, 
+		I915_GEM_DOMAIN_INSTRUCTION, 0,
+		0);
+
+	OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
+	OUT_BATCH(0);
+}
+
+/*
+ * URB layout for Xv on GEN7 
+ * ----------------------------------------
+ * | PS Push Constants (8KB) | VS entries |
+ * ----------------------------------------
+ */
+static void
+gen7_upload_urb(ScrnInfoPtr scrn)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
+	OUT_BATCH(8); /* in 1KBs */
+
+	OUT_BATCH(GEN7_3DSTATE_URB_VS | (2 - 2));
+	OUT_BATCH(
+		(32 << GEN7_URB_ENTRY_NUMBER_SHIFT) | /* at least 32 */
+		(2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
+		(1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+
+	OUT_BATCH(GEN7_3DSTATE_URB_GS | (2 - 2));
+	OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
+		(1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+
+	OUT_BATCH(GEN7_3DSTATE_URB_HS | (2 - 2));
+	OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
+		(2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+
+	OUT_BATCH(GEN7_3DSTATE_URB_DS | (2 - 2));
+	OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
+		(2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+}
+
+static void
+gen7_upload_cc_state_pointers(ScrnInfoPtr scrn)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2));
+	OUT_RELOC(intel->video.gen4_cc_bo,
+		I915_GEM_DOMAIN_INSTRUCTION, 0,
+		1);
+
+	OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
+	OUT_RELOC(intel->video.gen6_blend_bo,
+		I915_GEM_DOMAIN_INSTRUCTION, 0,
+		1);
+
+	OUT_BATCH(GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2));
+	OUT_RELOC(intel->video.gen6_depth_stencil_bo,
+		I915_GEM_DOMAIN_INSTRUCTION, 0, 
+		1);
+}
+
+static void
+gen7_upload_sampler_state_pointers(ScrnInfoPtr scrn)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
+	OUT_RELOC(intel->video.gen4_sampler_bo,
+		I915_GEM_DOMAIN_INSTRUCTION, 0,
+		0);
+}
+
+static void 
+gen7_upload_bypass_states(ScrnInfoPtr scrn)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	/* bypass GS */
+	OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (7 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
+	OUT_BATCH(0); /* without GS kernel */
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0); /* pass-through */
+
+	OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
+	OUT_BATCH(0);
+
+	/* disable HS */
+	OUT_BATCH(GEN7_3DSTATE_CONSTANT_HS | (7 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_HS | (7 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
+	OUT_BATCH(0);
+
+	/* Disable TE */
+	OUT_BATCH(GEN7_3DSTATE_TE | (4 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	/* Disable DS */
+	OUT_BATCH(GEN7_3DSTATE_CONSTANT_DS | (7 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_DS | (6 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
+	OUT_BATCH(0);
+
+	/* Disable STREAMOUT */
+	OUT_BATCH(GEN7_3DSTATE_STREAMOUT | (3 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+}
+
+static void 
+gen7_upload_vs_state(ScrnInfoPtr scrn)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	/* disable VS constant buffer */
+	OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (7 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	
+	OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
+	OUT_BATCH(0); /* without VS kernel */
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0); /* pass-through */
+}
+
+static void 
+gen7_upload_sf_state(ScrnInfoPtr scrn)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	OUT_BATCH(GEN7_3DSTATE_SBE | (14 - 2));
+	OUT_BATCH((1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
+		(1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
+		(0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0); /* DW4 */
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0); /* DW9 */
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN6_3DSTATE_SF | (7 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
+	OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+}
+
+static void 
+gen7_upload_wm_state(ScrnInfoPtr scrn, Bool is_packed)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	/* disable WM constant buffer */
+	OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (7 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN6_3DSTATE_WM | (3 - 2));
+	OUT_BATCH(GEN7_WM_DISPATCH_ENABLE |
+		GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_PS | (8 - 2));
+
+	if (is_packed) {
+		OUT_RELOC(intel->video.wm_prog_packed_bo,
+			I915_GEM_DOMAIN_INSTRUCTION, 0,
+			0);
+		OUT_BATCH((1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
+			(2 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+	} else {
+		OUT_RELOC(intel->video.wm_prog_planar_bo,
+			I915_GEM_DOMAIN_INSTRUCTION, 0,
+			0);
+		OUT_BATCH((1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
+			(7 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+	}
+
+	OUT_BATCH(0); /* scratch space base offset */
+	OUT_BATCH(
+		((86 - 1) << GEN7_PS_MAX_THREADS_SHIFT) |
+		GEN7_PS_ATTRIBUTE_ENABLE |
+		GEN7_PS_16_DISPATCH_ENABLE);
+	OUT_BATCH(
+		(6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0));
+	OUT_BATCH(0); /* kernel 1 pointer */
+	OUT_BATCH(0); /* kernel 2 pointer */
+}
+
+static void
+gen7_upload_binding_table(ScrnInfoPtr scrn, uint32_t ps_binding_table_offset)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
+	OUT_BATCH(ps_binding_table_offset);
+}
+
+static void
+gen7_upload_depth_buffer_state(ScrnInfoPtr scrn)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
+	OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
+		(BRW_SURFACE_NULL << 29));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+}
+
+static void 
+gen7_upload_vertex_buffer(ScrnInfoPtr scrn, drm_intel_bo *vertex_bo, uint32_t end_address_offset)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	/* Set up the pointer to our vertex buffer */
+	OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | (5 - 2));
+	/* four 32-bit floats per vertex */
+	OUT_BATCH((0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
+		GEN6_VB0_VERTEXDATA | 
+		GEN7_VB0_ADDRESS_MODIFYENABLE |
+		((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
+	OUT_RELOC(vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
+	OUT_RELOC(vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, end_address_offset);
+	OUT_BATCH(0);	/* reserved */
+}
+
+static void
+gen7_upload_primitive(ScrnInfoPtr scrn)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	OUT_BATCH(BRW_3DPRIMITIVE | (7 - 2));
+	OUT_BATCH(_3DPRIM_RECTLIST |
+		GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
+	OUT_BATCH(3); /* vertex count per instance */
+	OUT_BATCH(0); /* start vertex offset */
+	OUT_BATCH(1); /* single instance */
+	OUT_BATCH(0); /* start instance location */
+	OUT_BATCH(0);
+}
+
+static void
+gen7_emit_video_setup(ScrnInfoPtr scrn,
+		drm_intel_bo *surface_state_binding_table_bo, int n_src_surf,
+		PixmapPtr pixmap,
+		drm_intel_bo *vertex_bo, uint32_t end_address_offset)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	assert(n_src_surf == 1 || n_src_surf == 6);
+	IntelEmitInvarientState(scrn);
+	intel->last_3d = LAST_3D_VIDEO;
+
+	gen7_upload_invarient_states(scrn);
+	gen6_upload_state_base_address(scrn, surface_state_binding_table_bo);
+	gen7_upload_viewport_state_pointers(scrn);
+	gen7_upload_urb(scrn);
+	gen7_upload_cc_state_pointers(scrn);
+	gen7_upload_sampler_state_pointers(scrn);
+	gen7_upload_bypass_states(scrn);
+	gen7_upload_vs_state(scrn);
+	gen6_upload_clip_state(scrn);
+	gen7_upload_sf_state(scrn);
+	gen7_upload_wm_state(scrn, n_src_surf == 1 ? TRUE : FALSE);
+	gen7_upload_binding_table(scrn, (n_src_surf + 1) * SURFACE_STATE_PADDED_SIZE);
+	gen7_upload_depth_buffer_state(scrn);
+	gen6_upload_drawing_rectangle(scrn, pixmap);
+	gen6_upload_vertex_element_state(scrn);
+	gen7_upload_vertex_buffer(scrn, vertex_bo, end_address_offset);
+	gen7_upload_primitive(scrn);
 }
 
 void Gen6DisplayVideoTextured(ScrnInfoPtr scrn,
@@ -1866,13 +2279,19 @@  void Gen6DisplayVideoTextured(ScrnInfoPtr scrn,
 					uint32_t, int, 
 					int, int, uint32_t, 
 					drm_intel_bo *, uint32_t);
+	void (*emit_video_setup)(ScrnInfoPtr,
+				drm_intel_bo *, int,
+				PixmapPtr,
+				drm_intel_bo *, uint32_t);
 
 	if (INTEL_INFO(intel)->gen >= 70) {
 		create_dst_surface_state = gen7_create_dst_surface_state;
 		create_src_surface_state = gen7_create_src_surface_state;
+		emit_video_setup = gen7_emit_video_setup;
 	} else {
 		create_dst_surface_state = i965_create_dst_surface_state;
 		create_src_surface_state = i965_create_src_surface_state;
+		emit_video_setup = gen6_emit_video_setup;
 	}
 
 	src_surf_base[0] = adaptor_priv->YBufOffset;
@@ -2009,30 +2428,9 @@  void Gen6DisplayVideoTextured(ScrnInfoPtr scrn,
 			intel_batch_submit(scrn);
 
 		intel_batch_start_atomic(scrn, 200);
-		gen6_emit_video_setup(scrn, surface_state_binding_table_bo, n_src_surf, pixmap);
-
-		/* Set up the pointer to our vertex buffer */
-		OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | (5 - 2));
-		/* four 32-bit floats per vertex */
-		OUT_BATCH((0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
-			GEN6_VB0_VERTEXDATA | 
-			((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
-		OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
-		OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, i * 4);
-		OUT_BATCH(0);	/* reserved */
-
-		OUT_BATCH(BRW_3DPRIMITIVE | 
-			BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL | 
-			(_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) | 
-			(0 << 9) | /* Internal Vertex Count */
-			(6 - 2));
-		OUT_BATCH(3);	/* vertex count per instance */
-		OUT_BATCH(0);	/* start vertex offset */
-		OUT_BATCH(1);	/* single instance */
-		OUT_BATCH(0);	/* start instance location */
-		OUT_BATCH(0);	/* index buffer offset, ignored */
-
+		emit_video_setup(scrn, surface_state_binding_table_bo, n_src_surf, pixmap, vb_bo, i * 4);
 		intel_batch_end_atomic(scrn);
+
 		drm_intel_bo_unreference(vb_bo);
 	}