From patchwork Thu Jul 14 21:21:21 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kenneth Graunke X-Patchwork-Id: 975932 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p6ELSqFW019790 for ; Thu, 14 Jul 2011 21:29:12 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D60CD9F374 for ; Thu, 14 Jul 2011 14:28:52 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from homiemail-a6.g.dreamhost.com (mailbigip.dreamhost.com [208.97.132.5]) by gabe.freedesktop.org (Postfix) with ESMTP id 487599E98A for ; Thu, 14 Jul 2011 14:24:46 -0700 (PDT) Received: from homiemail-a6.g.dreamhost.com (localhost [127.0.0.1]) by homiemail-a6.g.dreamhost.com (Postfix) with ESMTP id DEC3259807B; Thu, 14 Jul 2011 14:24:45 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=whitecape.org; h=from:to:cc :subject:date:message-id:in-reply-to:references; q=dns; s= whitecape.org; b=AqVFAactcoVm9SUn9EsREyjlMfXOq1mvSnitYOf2WIPt1ur FW0mMf+uUWgaSJZKdPuZfMT8hqUwHrppmqofylbmIM0gyKP32ZTAhUMA4HwRBO7z nqSB955Wt0WoWdg0lHhMPkbDvkDFIj0RsbXUlHptQr/6uustV9HVlrVdY8hs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=whitecape.org; h=from:to :cc:subject:date:message-id:in-reply-to:references; s= whitecape.org; bh=GZSLEiqn3ZXtWlTNibsxAm231Sw=; b=uOXtIV13tGDdcy VvSps6w4h0OF350V6jCjwE/tS2b/x9sB7eU3/dr0cvaarYa/7ME1DSWOa0j63T2x uacES4lZtqOIbDxNASDcOqFERKG5wGvvX+7hVGTFdYau786Tbg0iuzYsnwMMrV4Q Y3r+kTFIWm/9rFN1JW2/BMU+loAVs= Received: from localhost (fruit.freedesktop.org [131.252.210.190]) (using TLSv1 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: kenneth@whitecape.org) by homiemail-a6.g.dreamhost.com (Postfix) with ESMTPSA id 8181959806C; Thu, 14 Jul 2011 14:24:42 -0700 (PDT) From: Kenneth Graunke To: intel-gfx@lists.freedesktop.org Date: Thu, 14 Jul 2011 14:21:21 -0700 Message-Id: <1310678483-7494-9-git-send-email-kenneth@whitecape.org> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1310678483-7494-1-git-send-email-kenneth@whitecape.org> References: <1310678483-7494-1-git-send-email-kenneth@whitecape.org> Subject: [Intel-gfx] [PATCH 08/10] render: Use Ivybridge variants for 3D pipeline setup. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 14 Jul 2011 21:29:13 +0000 (UTC) Signed-off-by: Kenneth Graunke --- src/i965_render.c | 50 +++++++++++++++++++++++++++++++++++++++----------- 1 files changed, 39 insertions(+), 11 deletions(-) diff --git a/src/i965_render.c b/src/i965_render.c index 17e35c9..5222d1c 100644 --- a/src/i965_render.c +++ b/src/i965_render.c @@ -2569,7 +2569,11 @@ gen6_composite_cc_state_pointers(intel_screen_private *intel, cc_bo = render_state->cc_state_bo; depth_stencil_bo = render_state->gen6_depth_stencil_bo; } - gen6_upload_cc_state_pointers(intel, render_state->gen6_blend_bo, cc_bo, depth_stencil_bo, blend_offset); + if (INTEL_INFO(intel)->gen >= 70) { + gen7_upload_cc_state_pointers(intel, render_state->gen6_blend_bo, cc_bo, depth_stencil_bo, blend_offset); + } else { + gen6_upload_cc_state_pointers(intel, render_state->gen6_blend_bo, cc_bo, depth_stencil_bo, blend_offset); + } intel->gen6_render_state.blend = blend_offset; } @@ -2583,18 +2587,26 @@ gen6_composite_sampler_state_pointers(intel_screen_private *intel, intel->gen6_render_state.samplers = bo; - gen6_upload_sampler_state_pointers(intel, bo); + if (INTEL_INFO(intel)->gen >= 70) + gen7_upload_sampler_state_pointers(intel, bo); + else + gen6_upload_sampler_state_pointers(intel, bo); } static void gen6_composite_wm_constants(intel_screen_private *intel) { + Bool ivb = INTEL_INFO(intel)->gen >= 70; /* disable WM constant buffer */ - OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (5 - 2)); + OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | ((ivb ? 7 : 5) - 2)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); + if (ivb) { + OUT_BATCH(0); + OUT_BATCH(0); + } } static void @@ -2608,7 +2620,10 @@ gen6_composite_sf_state(intel_screen_private *intel, intel->gen6_render_state.num_sf_outputs = num_sf_outputs; - gen6_upload_sf_state(intel, num_sf_outputs, 1); + if (INTEL_INFO(intel)->gen >= 70) + gen7_upload_sf_state(intel, num_sf_outputs, 1); + else + gen6_upload_sf_state(intel, num_sf_outputs, 1); } static void @@ -2754,20 +2769,30 @@ gen6_emit_composite_state(struct intel_screen_private *intel) sampler_state_extend_t mask_extend = composite_op->mask_extend; Bool is_affine = composite_op->is_affine; Bool has_mask = intel->render_mask != NULL; + Bool ivb = INTEL_INFO(intel)->gen >= 70; uint32_t src, dst; drm_intel_bo *ps_sampler_state_bo = render->ps_sampler_state_bo[src_filter][src_extend][mask_filter][mask_extend]; intel->needs_render_state_emit = FALSE; if (intel->needs_3d_invariant) { gen6_upload_invariant_states(intel); - gen6_upload_viewport_state_pointers(intel, render->cc_vp_bo); - gen6_upload_urb(intel); + if (ivb) { + gen7_upload_viewport_state_pointers(intel, render->cc_vp_bo); + gen7_upload_urb(intel); + gen7_upload_bypass_states(intel); + gen7_upload_depth_buffer_state(intel); + } else { + gen6_upload_invariant_states(intel); + gen6_upload_viewport_state_pointers(intel, render->cc_vp_bo); + gen6_upload_urb(intel); + + gen6_upload_gs_state(intel); + gen6_upload_depth_buffer_state(intel); + } + gen6_composite_wm_constants(intel); gen6_upload_vs_state(intel); - gen6_upload_gs_state(intel); gen6_upload_clip_state(intel); - gen6_composite_wm_constants(intel); - gen6_upload_depth_buffer_state(intel); intel->needs_3d_invariant = FALSE; } @@ -2787,8 +2812,11 @@ gen6_emit_composite_state(struct intel_screen_private *intel) gen6_composite_wm_state(intel, has_mask, render->wm_kernel_bo[composite_op->wm_kernel]); - gen6_upload_binding_table(intel, intel->surface_table); - + if (ivb) { + gen7_upload_binding_table(intel, intel->surface_table); + } else { + gen6_upload_binding_table(intel, intel->surface_table); + } gen6_composite_drawing_rectangle(intel, intel->render_dest); gen6_composite_vertex_element_state(intel, has_mask, is_affine); }