From patchwork Thu Jul 28 18:48:03 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 1017512 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p6SImUiq016277 for ; Thu, 28 Jul 2011 18:48:50 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B8D1DA0282 for ; Thu, 28 Jul 2011 11:48:30 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from oproxy4-pub.bluehost.com (oproxy4-pub.bluehost.com [69.89.21.11]) by gabe.freedesktop.org (Postfix) with SMTP id 041739E776 for ; Thu, 28 Jul 2011 11:48:09 -0700 (PDT) Received: (qmail 15718 invoked by uid 0); 28 Jul 2011 18:48:09 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by cpoproxy1.bluehost.com with SMTP; 28 Jul 2011 18:48:09 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=Message-Id:Date:Subject:Cc:To:From; bh=YkcNierCDiL/iMWKU5ZkSTl28F9bjTnyqtiSCrwLqHs=; b=XqIG20rog8O5bI539FPNPkwLLoL5QNNKcUex1CJCDER4cc6r9oNEhlaYH0jZDoA7BZeJO19pFKNAkilAwQcTsdpKYe5PIu73QkwG5ClBl/dBL19U1J8bTO44pdrlQayA; Received: from c-67-161-37-189.hsd1.ca.comcast.net ([67.161.37.189] helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.69) (envelope-from ) id 1QmVct-0000AJ-8Q; Thu, 28 Jul 2011 12:48:07 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Thu, 28 Jul 2011 11:48:03 -0700 Message-Id: <1311878883-9946-1-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.7.4.1 X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH] drm/i915: make sure plane control reg changes take effect X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Thu, 28 Jul 2011 18:48:50 +0000 (UTC) After writing to the plane control reg we need to write to the surface reg to trigger the double buffered register latch. v2: write DSPADDR too to cover pre-965 chipsets Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 7 ++ drivers/gpu/drm/i915/intel_display.c | 143 ++++++++++++++++++++++++---------- 4 files changed, 112 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index ce045a8..60e4b9e 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -62,7 +62,7 @@ module_param_named(semaphores, i915_semaphores, int, 0600); MODULE_PARM_DESC(semaphores, "Use semaphores for inter-ring sync (default: false)"); -unsigned int i915_enable_rc6 __read_mostly = 0; +unsigned int i915_enable_rc6 __read_mostly = 1; module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); MODULE_PARM_DESC(i915_enable_rc6, "Enable power-saving render C-state 6 (default: true)"); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 78cdd15..4f24e72 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -337,6 +337,8 @@ typedef struct drm_i915_private { int cfb_y; struct intel_fbc_work *fbc_work; + int planes_enabled; + struct intel_opregion opregion; /* overlay */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7377ae4..ae28549 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3081,6 +3081,13 @@ #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) #define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31) +#define SOUTH_CHICKEN1 0xc2000 +#define FDIA_PHASE_SYNC_OVR (1<<19) +#define FDIA_PHASE_SYNC_EN (1<<18) +#define FDIB_PHASE_SYNC_OVR (1<<17) +#define FDIB_PHASE_SYNC_EN (1<<16) +#define FDIC_PHASE_SYNC_OVR (1<<15) +#define FDIC_PHASE_SYNC_EN (1<<14) #define SOUTH_CHICKEN2 0xc2004 #define DPLS_EDP_PPS_FIX_DIS (1<<0) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 32ffde2..30379df 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1333,6 +1333,9 @@ static void intel_disable_plane(struct drm_i915_private *dev_priv, return; I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); + /* Flush out the double buffered plane control reg */ + I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); + I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); intel_flush_display_plane(dev_priv, plane); intel_wait_for_vblank(dev_priv->dev, pipe); } @@ -1370,7 +1373,7 @@ static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, val = I915_READ(reg); if (ADPA_PIPE_ENABLED(val, pipe)) I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); - +#if 0 reg = PCH_LVDS; val = I915_READ(reg); if (LVDS_PIPE_ENABLED(val, pipe)) { @@ -1378,7 +1381,7 @@ static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, POSTING_READ(reg); udelay(100); } - +#endif disable_pch_hdmi(dev_priv, pipe, HDMIB); disable_pch_hdmi(dev_priv, pipe, HDMIC); disable_pch_hdmi(dev_priv, pipe, HDMID); @@ -2295,6 +2298,23 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc) I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN); + } else if (HAS_PCH_CPT(dev)) { + u32 flags; + switch (pipe) { + case 0: + flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN; + break; + case 2: + flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN; + break; + case 3: + flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN; + break; + default: + break; + } + I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ + I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ } reg = FDI_RX_IIR(pipe); @@ -2652,6 +2672,23 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc) I915_WRITE(FDI_RX_CHICKEN(pipe), I915_READ(FDI_RX_CHICKEN(pipe) & ~FDI_RX_PHASE_SYNC_POINTER_EN)); + } else if (HAS_PCH_CPT(dev)) { + u32 flags; + switch (pipe) { + case 0: + flags = FDIA_PHASE_SYNC_OVR; + break; + case 2: + flags = FDIA_PHASE_SYNC_OVR; + break; + case 3: + flags = FDIA_PHASE_SYNC_OVR; + break; + default: + break; + } + I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ + I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ } /* still set train pattern 1 */ @@ -2919,6 +2956,10 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) /* disable TRANS_DP_CTL */ reg = TRANS_DP_CTL(pipe); temp = I915_READ(reg); + temp &= ~TRANS_DP_PORT_SEL_MASK; + temp |= TRANS_DP_PORT_SEL_NONE; + I915_WRITE(reg, temp); + intel_wait_for_vblank(dev, pipe); temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); temp |= TRANS_DP_PORT_SEL_NONE; I915_WRITE(reg, temp); @@ -4328,51 +4369,20 @@ static void ironlake_update_wm(struct drm_device *dev) */ } -static void sandybridge_update_wm(struct drm_device *dev) +static void snb_disable_lpwm(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ - int fbc_wm, plane_wm, cursor_wm; - unsigned int enabled; - enabled = 0; - if (g4x_compute_wm0(dev, 0, - &sandybridge_display_wm_info, latency, - &sandybridge_cursor_wm_info, latency, - &plane_wm, &cursor_wm)) { - I915_WRITE(WM0_PIPEA_ILK, - (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); - DRM_DEBUG_KMS("FIFO watermarks For pipe A -" - " plane %d, " "cursor: %d\n", - plane_wm, cursor_wm); - enabled |= 1; - } - - if (g4x_compute_wm0(dev, 1, - &sandybridge_display_wm_info, latency, - &sandybridge_cursor_wm_info, latency, - &plane_wm, &cursor_wm)) { - I915_WRITE(WM0_PIPEB_ILK, - (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); - DRM_DEBUG_KMS("FIFO watermarks For pipe B -" - " plane %d, cursor: %d\n", - plane_wm, cursor_wm); - enabled |= 2; - } - - /* - * Calculate and update the self-refresh watermark only when one - * display plane is used. - * - * SNB support 3 levels of watermark. - * - * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, - * and disabled in the descending order - * - */ I915_WRITE(WM3_LP_ILK, 0); I915_WRITE(WM2_LP_ILK, 0); I915_WRITE(WM1_LP_ILK, 0); +} + +void snb_enable_lpwm(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + int fbc_wm, plane_wm, cursor_wm; + int enabled = dev_priv->planes_enabled; if (!single_plane_enabled(enabled)) return; @@ -4424,6 +4434,55 @@ static void sandybridge_update_wm(struct drm_device *dev) cursor_wm); } +static void sandybridge_update_wm(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ + int plane_wm, cursor_wm; + unsigned int enabled; + + enabled = 0; + if (g4x_compute_wm0(dev, 0, + &sandybridge_display_wm_info, latency, + &sandybridge_cursor_wm_info, latency, + &plane_wm, &cursor_wm)) { + I915_WRITE(WM0_PIPEA_ILK, + (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); + DRM_DEBUG_KMS("FIFO watermarks For pipe A -" + " plane %d, " "cursor: %d\n", + plane_wm, cursor_wm); + enabled |= 1; + } + + if (g4x_compute_wm0(dev, 1, + &sandybridge_display_wm_info, latency, + &sandybridge_cursor_wm_info, latency, + &plane_wm, &cursor_wm)) { + I915_WRITE(WM0_PIPEB_ILK, + (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); + DRM_DEBUG_KMS("FIFO watermarks For pipe B -" + " plane %d, cursor: %d\n", + plane_wm, cursor_wm); + enabled |= 2; + } + + /* + * Calculate and update the self-refresh watermark only when one + * display plane is used. + * + * SNB support 3 levels of watermark. + * + * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, + * and disabled in the descending order + * + */ + snb_disable_lpwm(dev); + + dev_priv->planes_enabled = enabled; + + snb_enable_lpwm(dev); +} + /** * intel_update_watermarks - update FIFO watermark values based on current modes * @@ -5515,6 +5574,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, drm_vblank_post_modeset(dev, pipe); + intel_crtc->dpms_mode = DRM_MODE_DPMS_ON; + return ret; }