From patchwork Thu Jul 28 19:55:13 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 1017592 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p6SJtkqq017905 for ; Thu, 28 Jul 2011 19:56:08 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9D5A9A0310 for ; Thu, 28 Jul 2011 12:55:45 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from oproxy1-pub.bluehost.com (oproxy1-pub.bluehost.com [66.147.249.253]) by gabe.freedesktop.org (Postfix) with SMTP id DE3B19E76E for ; Thu, 28 Jul 2011 12:55:24 -0700 (PDT) Received: (qmail 29143 invoked by uid 0); 28 Jul 2011 19:55:24 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by oproxy1.bluehost.com with SMTP; 28 Jul 2011 19:55:24 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=Message-Id:Date:Subject:Cc:To:From; bh=+yIoT9gS0NBWCC/12KrT9E3UCvvfNfenmafT+zYI03A=; b=EKbrsCOlSg9vmQkykr7LY5iFZr8b8mfhNDXu5Qdq/wHMBNB32CN8RHLTy64Nurz4PMF6gsbSKGxFMtbNrwBw2AYTWdw8sAWy2RWG/K8lwLrUbzmHViTS8slNY+rfuH7W; Received: from c-67-161-37-189.hsd1.ca.comcast.net ([67.161.37.189] helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.69) (envelope-from ) id 1QmWfx-0001Xp-Vz; Thu, 28 Jul 2011 13:55:22 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Thu, 28 Jul 2011 12:55:13 -0700 Message-Id: <1311882914-11676-1-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.7.4.1 X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH 1/2] drm/i915: apply phase pointer override on SNB+ too X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 28 Jul 2011 19:56:08 +0000 (UTC) These bits moved around on SNB and above. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ drivers/gpu/drm/i915/intel_display.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7377ae4..ae28549 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3081,6 +3081,13 @@ #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) #define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31) +#define SOUTH_CHICKEN1 0xc2000 +#define FDIA_PHASE_SYNC_OVR (1<<19) +#define FDIA_PHASE_SYNC_EN (1<<18) +#define FDIB_PHASE_SYNC_OVR (1<<17) +#define FDIB_PHASE_SYNC_EN (1<<16) +#define FDIC_PHASE_SYNC_OVR (1<<15) +#define FDIC_PHASE_SYNC_EN (1<<14) #define SOUTH_CHICKEN2 0xc2004 #define DPLS_EDP_PPS_FIX_DIS (1<<0) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 73bf235..2a367de 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2295,6 +2295,23 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc) I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN); + } else if (HAS_PCH_CPT(dev)) { + u32 flags; + switch (pipe) { + case 0: + flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN; + break; + case 2: + flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN; + break; + case 3: + flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN; + break; + default: + break; + } + I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ + I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ } reg = FDI_RX_IIR(pipe); @@ -2652,6 +2669,23 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc) I915_WRITE(FDI_RX_CHICKEN(pipe), I915_READ(FDI_RX_CHICKEN(pipe) & ~FDI_RX_PHASE_SYNC_POINTER_EN)); + } else if (HAS_PCH_CPT(dev)) { + u32 flags; + switch (pipe) { + case 0: + flags = FDIA_PHASE_SYNC_OVR; + break; + case 2: + flags = FDIA_PHASE_SYNC_OVR; + break; + case 3: + flags = FDIA_PHASE_SYNC_OVR; + break; + default: + break; + } + I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ + I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ } /* still set train pattern 1 */