From patchwork Thu Sep 8 12:00:20 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1129592 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p88D0coo001198 for ; Thu, 8 Sep 2011 13:00:59 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A82C56B2E1 for ; Thu, 8 Sep 2011 06:00:36 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ww0-f43.google.com (mail-ww0-f43.google.com [74.125.82.43]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E1A29F314 for ; Thu, 8 Sep 2011 06:00:15 -0700 (PDT) Received: by wwe32 with SMTP id 32so679251wwe.12 for ; Thu, 08 Sep 2011 06:00:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer; bh=Ru6gVPkjWhN8KhQq63oWfee1q6UUShfPm4U6hqAjPh4=; b=Ga4pxJl8pbGzJxnyEZdj/yT1ZuN98kxZI4IyLBHOewjbE31HGbxK9UoLZ1mr0D1iut 3w+6ytRzFIw5MHlU0+vy5PUBTaN3CcI+eVMUe1FLrnhw9veG6CbsB2LpZAY7HmOMJl0f YozhJbdpB9q5RK0cWUjWMq/F2SBlNJfJArnNo= Received: by 10.227.201.83 with SMTP id ez19mr718985wbb.26.1315486814741; Thu, 08 Sep 2011 06:00:14 -0700 (PDT) Received: from localhost.localdomain (178-83-130-250.dynamic.hispeed.ch [178.83.130.250]) by mx.google.com with ESMTPS id ev5sm4161718wbb.11.2011.09.08.06.00.13 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 08 Sep 2011 06:00:14 -0700 (PDT) From: Daniel Vetter To: intel-gfx@lists.freedesktop.org Date: Thu, 8 Sep 2011 14:00:20 +0200 Message-Id: <1315483222-2195-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.6 Cc: Daniel Vetter , Ben Widawsky Subject: [Intel-gfx] [PATCH 1/3] drm/i915: close PM interrupt masking races in the irq handler X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Thu, 08 Sep 2011 13:00:59 +0000 (UTC) Quoting Chris Wilson's more concise description: "Ah I think I see the problem. As you point out we only mask the current interrupt received, so that if we have a task pending (and so IMR != 0) we actually unmask the pending interrupt and so could receive it again before the tasklet is finally kicked off by the grumpy scheduler." We need the hw to issue PM interrupts A, B, A while the scheduler is hating us and refuses to run the rps work item. On receiving PM interrupt A we hit the WARN because dev_priv->pm_iir == PM_A | PM_B Also add a posting read as suggested by Chris to ensure proper ordering of the writes to PMIMR and PMIIR. Just in case somebody weakens write ordering. Signed-off-by: Daniel Vetter Reviewed-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_irq.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 9cbb0cd..2fdd9f9 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -536,8 +536,9 @@ static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) unsigned long flags; spin_lock_irqsave(&dev_priv->rps_lock, flags); WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); - I915_WRITE(GEN6_PMIMR, pm_iir); dev_priv->pm_iir |= pm_iir; + I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); + POSTING_READ(GEN6_PMIMR); spin_unlock_irqrestore(&dev_priv->rps_lock, flags); queue_work(dev_priv->wq, &dev_priv->rps_work); } @@ -649,8 +650,9 @@ static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) unsigned long flags; spin_lock_irqsave(&dev_priv->rps_lock, flags); WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); - I915_WRITE(GEN6_PMIMR, pm_iir); dev_priv->pm_iir |= pm_iir; + I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); + POSTING_READ(GEN6_PMIMR); spin_unlock_irqrestore(&dev_priv->rps_lock, flags); queue_work(dev_priv->wq, &dev_priv->rps_work); }