From patchwork Wed Jul 11 14:29:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1184331 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 9F8C23FC5A for ; Wed, 11 Jul 2012 16:35:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 72A21A0EB1 for ; Wed, 11 Jul 2012 09:35:08 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 00EFD9EED2 for ; Wed, 11 Jul 2012 08:36:58 -0700 (PDT) Received: by mail-we0-f177.google.com with SMTP id r3so960506wey.36 for ; Wed, 11 Jul 2012 08:36:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=m1fRWteByqE5qGB5s55UTyp4B1x/Wyr0BX8IOPBpRLA=; b=lPTV6fELZp2cT6qkF30Hh67vVImXTyWYJ1P9ZMNuU/W5zsADoQ3GZYFYfB2jTTzaVk W7WORbaktFxHGrYLQPHSqvattdd0n6osOUtRXNlYRRLhXmrNEUXZ9UM36BYh2XR2+cd+ aCDX7+P2L3VIsqYifBloUZ8K4hwkhRnFK0zp8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=m1fRWteByqE5qGB5s55UTyp4B1x/Wyr0BX8IOPBpRLA=; b=pLZ+dlb2gzWSsgPhH5plp/SrCcPfioIGB1XcFHlwmX5UYHy/ZKvYWjsBKauNM+7XSL CXacIndOSsQ5Qx4P+ybQ/nNwy/WynjnyWwp5MVBPb7qeIHq69NUb179NF2YmF909SFoB N5HTvt74d5c5dNFFy51Uz6twoDufo9Q1KKjYzYven7jJb+uoHKNLigXlViMKAn3LbwAk odrC397sieQ3PN7iQFfcLvf9kL3y3mPyc7fVBolCuj9pbW1Eb958iP6VoTlb2YnaEdS8 BpWoY3iyme16Lu//WrO1Y1tSESpjG/jmHwbpJICruo8SJfGkYHMW9FVxWjFoWdUfuuN2 Ujyw== Received: by 10.180.86.106 with SMTP id o10mr48095259wiz.22.1342021018600; Wed, 11 Jul 2012 08:36:58 -0700 (PDT) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id bc2sm5777080wib.0.2012.07.11.08.36.57 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 11 Jul 2012 08:36:57 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 11 Jul 2012 16:29:01 +0200 Message-Id: <1342016944-23395-79-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1342016944-23395-1-git-send-email-daniel.vetter@ffwll.ch> References: <1342016944-23395-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQlnSQOIDmZyZGij/sdwO0Z8Qz9UKDh6JHXPRUl6ipjWlpQXMsxDrdqFi4CYIpaSwWby8Ghz Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 78/81] drm/i915: clean up the cpu edp pll special case X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org By using the new pre_enabel/post_disable functions. To ensure that we only frob the cpu edp pll while the pipe is off add the relevant asserts. Thanks to the new output state staging, this is now really easy. Signed-Off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 74 ++++++++++++++------------------------ 1 files changed, 27 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8f0bb2b..6d3f3df 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -838,9 +838,6 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, } } -static void ironlake_edp_pll_on(struct drm_encoder *encoder); -static void ironlake_edp_pll_off(struct drm_encoder *encoder); - static void intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) @@ -851,14 +848,6 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_crtc *crtc = intel_dp->base.base.crtc; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - /* Turn on the eDP PLL if needed */ - if (is_edp(intel_dp)) { - if (!is_pch_edp(intel_dp)) - ironlake_edp_pll_on(encoder); - else - ironlake_edp_pll_off(encoder); - } - /* * There are four kinds of DP registers: * @@ -1219,12 +1208,16 @@ static void ironlake_edp_backlight_off(struct intel_dp *intel_dp) msleep(intel_dp->backlight_off_delay); } -static void ironlake_edp_pll_on(struct drm_encoder *encoder) +static void ironlake_edp_pll_on(struct intel_dp *intel_dp) { - struct drm_device *dev = encoder->dev; + struct drm_device *dev = intel_dp->base.base.dev; + struct drm_crtc *crtc = intel_dp->base.base.crtc; struct drm_i915_private *dev_priv = dev->dev_private; u32 dpa_ctl; + assert_pipe_disabled(dev_priv, + to_intel_crtc(crtc)->pipe); + DRM_DEBUG_KMS("\n"); dpa_ctl = I915_READ(DP_A); dpa_ctl |= DP_PLL_ENABLE; @@ -1233,12 +1226,16 @@ static void ironlake_edp_pll_on(struct drm_encoder *encoder) udelay(200); } -static void ironlake_edp_pll_off(struct drm_encoder *encoder) +static void ironlake_edp_pll_off(struct intel_dp *intel_dp) { - struct drm_device *dev = encoder->dev; + struct drm_device *dev = intel_dp->base.base.dev; + struct drm_crtc *crtc = intel_dp->base.base.crtc; struct drm_i915_private *dev_priv = dev->dev_private; u32 dpa_ctl; + assert_pipe_disabled(dev_priv, + to_intel_crtc(crtc)->pipe); + dpa_ctl = I915_READ(DP_A); dpa_ctl &= ~DP_PLL_ENABLE; I915_WRITE(DP_A, dpa_ctl); @@ -1339,6 +1336,14 @@ static void intel_disable_dp(struct intel_encoder *encoder) ironlake_edp_panel_vdd_off(intel_dp, false); } +static void intel_post_disable_dp(struct intel_encoder *encoder) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + + if (is_cpu_edp(intel_dp)) + ironlake_edp_pll_off(intel_dp); +} + static void intel_enable_dp(struct intel_encoder *encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); @@ -1358,39 +1363,12 @@ static void intel_enable_dp(struct intel_encoder *encoder) ironlake_edp_backlight_on(intel_dp); } -static void -intel_dp_dpms(struct drm_connector *connector, int mode) +static void intel_pre_enable_dp(struct intel_encoder *encoder) { - struct intel_dp *intel_dp = intel_attached_dp(connector); - - /* DP supports only 2 dpms states. */ - if (mode != DRM_MODE_DPMS_ON) - mode = DRM_MODE_DPMS_OFF; - - if (mode == connector->dpms) - return; - - connector->dpms = mode; - - /* Only need to change hw state when actually enabled */ - if (!intel_dp->base.base.crtc) { - intel_dp->base.connectors_active = false; - return; - } - - if (mode != DRM_MODE_DPMS_ON) { - intel_encoder_dpms(&intel_dp->base, mode); - - if (is_cpu_edp(intel_dp)) - ironlake_edp_pll_off(&intel_dp->base.base); - } else { - if (is_cpu_edp(intel_dp)) - ironlake_edp_pll_on(&intel_dp->base.base); - - intel_encoder_dpms(&intel_dp->base, mode); - } + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); - intel_connector_check_state(to_intel_connector(connector)); + if (is_cpu_edp(intel_dp)) + ironlake_edp_pll_on(intel_dp); } /* @@ -2409,7 +2387,7 @@ static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { }; static const struct drm_connector_funcs intel_dp_connector_funcs = { - .dpms = intel_dp_dpms, + .dpms = intel_connector_dpms, .detect = intel_dp_detect, .fill_modes = drm_helper_probe_single_connector_modes, .set_property = intel_dp_set_property, @@ -2539,7 +2517,9 @@ intel_dp_init(struct drm_device *dev, int output_reg) drm_sysfs_connector_add(connector); intel_encoder->enable = intel_enable_dp; + intel_encoder->pre_enable = intel_pre_enable_dp; intel_encoder->disable = intel_disable_dp; + intel_encoder->post_disable = intel_post_disable_dp; intel_encoder->get_hw_state = intel_dp_get_hw_state; intel_connector->get_hw_state = intel_connector_get_hw_state;