From patchwork Wed Jul 11 14:29:02 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1184341 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 3DB133FC5A for ; Wed, 11 Jul 2012 16:35:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 28766A0D98 for ; Wed, 11 Jul 2012 09:35:59 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 26476A0E75 for ; Wed, 11 Jul 2012 08:36:59 -0700 (PDT) Received: by mail-we0-f177.google.com with SMTP id r3so960506wey.36 for ; Wed, 11 Jul 2012 08:37:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=aAHAdHCqRopFYfv3uFhurn5COS37Vccq6/M11pPJ/mg=; b=UKnYmdq0tGd+3llyEB+Jlj5LQxfhpUjTL7l/Kb+N6mJPH8flzEC//OW3UXontB/8qr VzMM8HKiF7qJfqu20TeUXgOS0Di22xK2gKG8tXjc4tYRlof9x6Sc3NEhZbWDSHH25GCr 99iOkXN2ZzrsCuWz0G+E4Kr9616nwfPKB5AfQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=aAHAdHCqRopFYfv3uFhurn5COS37Vccq6/M11pPJ/mg=; b=AmomXnMI7WO+g2+y6wf0R1ES+5g6PUXYcZfwCi19njQ9cFU5BCxRlCEom/sLdwhP23 KUmXJa0Z8RCrY6hmyY3CbSv0FFh5UMgLDodqEnm/9CC8BkWtNulqm7NN73rZ7K3lRDIi HoyT7m3WQ+mdvv4ukrLXqXvDNc3aphh2JXukBcwPHRO+UIQIvA92LoAOR1Z5jpUseyzZ p+qZF68OURNfbjS2J6Bj1c1wQVCwW4V12vZcskpKA2ieEcstWuHs5xdDrUKaAh90KVvH ahwglZJzKSSvx62oSoWazw3s1Kx6DQNLh2O5XJTQiGpVfnqTfF04FtInHiuH2Ntwecuo aIMQ== Received: by 10.180.99.232 with SMTP id et8mr9806230wib.11.1342021019917; Wed, 11 Jul 2012 08:36:59 -0700 (PDT) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id bc2sm5777080wib.0.2012.07.11.08.36.58 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 11 Jul 2012 08:36:59 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 11 Jul 2012 16:29:02 +0200 Message-Id: <1342016944-23395-80-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1342016944-23395-1-git-send-email-daniel.vetter@ffwll.ch> References: <1342016944-23395-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQm2Lo6LMt/+yW+KGCTa5rpiEeOFzHK910G9+4xRI1EOQVdOUp1tNj5DQDRZe7EJEJNfMvBY Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 79/81] drm/i915: robustify edp_pll_on/off X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org With the previous patch to clean up where exactly these two functions are getting called, this patch can tackle the enable/disable code itself: - WARN if the port enable bit is in the wrong state or if the edp pll bit is in the wrong state, just for paranoia's sake. - Don't disable the edp pll harder in the modeset functions just for fun. - Don't set the edp pll enable flag in intel_dp->DP in modeset, do that while changing the actual hw state. We do the same with the actual port enable bit, so this is a bit more consistent. - Track the current DP register value when setting things up and add some comments how intel_dp->DP is used in the disable code. Signed-Off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 25 ++++++++++++++----------- 1 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 6d3f3df..68fe1dd 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -919,7 +919,6 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, intel_dp->DP |= intel_crtc->pipe << 29; /* don't miss out required setting for eDP */ - intel_dp->DP |= DP_PLL_ENABLE; if (adjusted_mode->clock < 200000) intel_dp->DP |= DP_PLL_FREQ_160MHZ; else @@ -941,7 +940,6 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, if (is_cpu_edp(intel_dp)) { /* don't miss out required setting for eDP */ - intel_dp->DP |= DP_PLL_ENABLE; if (adjusted_mode->clock < 200000) intel_dp->DP |= DP_PLL_FREQ_160MHZ; else @@ -1220,8 +1218,11 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp) DRM_DEBUG_KMS("\n"); dpa_ctl = I915_READ(DP_A); - dpa_ctl |= DP_PLL_ENABLE; - I915_WRITE(DP_A, dpa_ctl); + WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); + WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); + + intel_dp->DP |= DP_PLL_ENABLE; + I915_WRITE(DP_A, intel_dp->DP); POSTING_READ(DP_A); udelay(200); } @@ -1237,6 +1238,13 @@ static void ironlake_edp_pll_off(struct intel_dp *intel_dp) to_intel_crtc(crtc)->pipe); dpa_ctl = I915_READ(DP_A); + WARN((dpa_ctl & DP_PLL_ENABLE) == 0, + "dp pll off, should be on\n"); + WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); + + /* We can't rely on the value tracked for the DP register in + * intel_dp->DP because link_down must not change that (otherwise link + * re-training will fail. */ dpa_ctl &= ~DP_PLL_ENABLE; I915_WRITE(DP_A, dpa_ctl); POSTING_READ(DP_A); @@ -1919,13 +1927,6 @@ intel_dp_link_down(struct intel_dp *intel_dp) DRM_DEBUG_KMS("\n"); - if (is_edp(intel_dp)) { - DP &= ~DP_PLL_ENABLE; - I915_WRITE(intel_dp->output_reg, DP); - POSTING_READ(intel_dp->output_reg); - udelay(100); - } - if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { DP &= ~DP_LINK_TRAIN_MASK_CPT; I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); @@ -2473,6 +2474,8 @@ intel_dp_init(struct drm_device *dev, int output_reg) return; intel_dp->output_reg = output_reg; + /* Preserve the current hw state. */ + intel_dp->DP = I915_READ(intel_dp->output_reg); intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); if (!intel_connector) {