From patchwork Fri Jul 13 06:16:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 1194001 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id A3F573FC5A for ; Fri, 13 Jul 2012 07:01:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 64A51A102A for ; Fri, 13 Jul 2012 00:01:46 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from cloud01.chad-versace.us (184-106-247-128.static.cloud-ips.com [184.106.247.128]) by gabe.freedesktop.org (Postfix) with ESMTP id DE651A0FDC for ; Thu, 12 Jul 2012 23:18:24 -0700 (PDT) Received: from localhost (localhost [127.0.0.1]) by cloud01.chad-versace.us (Postfix) with ESMTP id 9CA371810C9; Fri, 13 Jul 2012 06:21:01 +0000 (UTC) X-Virus-Scanned: amavisd-new at static.cloud-ips.com X-Spam-Flag: NO X-Spam-Score: -2.9 X-Spam-Level: X-Spam-Status: No, score=-2.9 tagged_above=-100 required=3.5 tests=[ALL_TRUSTED=-1, BAYES_00=-1.9] autolearn=ham Received: from cloud01.chad-versace.us ([127.0.0.1]) by localhost (cloud01.static.cloud-ips.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZcYyb8j9pfKl; Fri, 13 Jul 2012 06:20:56 +0000 (UTC) Received: from seagal.kumite (static-50-53-63-81.bvtn.or.frontiernet.net [50.53.63.81]) by cloud01.chad-versace.us (Postfix) with ESMTPSA id CEF5618106A; Fri, 13 Jul 2012 06:20:51 +0000 (UTC) From: Ben Widawsky To: intel-gfx@lists.freedesktop.org Date: Thu, 12 Jul 2012 23:16:15 -0700 Message-Id: <1342160176-1807-5-git-send-email-ben@bwidawsk.net> X-Mailer: git-send-email 1.7.11.1 In-Reply-To: <1342160176-1807-1-git-send-email-ben@bwidawsk.net> References: <1342160176-1807-1-git-send-email-ben@bwidawsk.net> Cc: Ben Widawsky Subject: [Intel-gfx] [PATCH 4/5] drm/i915: kill struct pipe_control X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org It's all redundant with the object now. Simply store that. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/intel_ringbuffer.c | 58 ++++++++------------------------- 1 file changed, 13 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 33d87ad..130a5a7 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -34,16 +34,6 @@ #include "i915_trace.h" #include "intel_drv.h" -/* - * 965+ support PIPE_CONTROL commands, which provide finer grained control - * over cache flushing. - */ -struct pipe_control { - struct drm_i915_gem_object *obj; - volatile u32 *cpu_page; - u32 gtt_offset; -}; - static inline int ring_space(struct intel_ring_buffer *ring) { int space = (ring->head & HEAD_ADDR) - (ring->tail + 8); @@ -176,8 +166,8 @@ gen4_render_ring_flush(struct intel_ring_buffer *ring, static int intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) { - struct pipe_control *pc = ring->private; - u32 scratch_addr = pc->gtt_offset + 128; + struct drm_i915_gem_object *obj = ring->private; + u32 scratch_addr = obj->gtt_offset + 128; int ret; @@ -214,8 +204,8 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, u32 invalidate_domains, u32 flush_domains) { u32 flags = 0; - struct pipe_control *pc = ring->private; - u32 scratch_addr = pc->gtt_offset + 128; + struct drm_i915_gem_object *obj = ring->private; + u32 scratch_addr = obj->gtt_offset + 128; int ret; /* Force SNB workarounds for PIPE_CONTROL flushes */ @@ -391,54 +381,32 @@ err_unref: static int init_pipe_control(struct intel_ring_buffer *ring) { - struct pipe_control *pc; struct drm_i915_gem_object *obj; - int ret; if (ring->private) return 0; - pc = kmalloc(sizeof(*pc), GFP_KERNEL); - if (!pc) - return -ENOMEM; - obj = ring_alloc_object(ring->dev); if (IS_ERR(obj)) { DRM_ERROR("Failed to allocate pipe control page\n"); - ret = PTR_ERR(obj); - goto err; + return PTR_ERR(obj); } - - pc->gtt_offset = obj->gtt_offset; - pc->cpu_page = obj->cpu_map; - if (pc->cpu_page == NULL) { - ret = -ENOMEM; - goto err; - } - - pc->obj = obj; - ring->private = pc; + ring->private = obj; return 0; - -err: - kfree(pc); - return ret; } static void cleanup_pipe_control(struct intel_ring_buffer *ring) { - struct pipe_control *pc = ring->private; struct drm_i915_gem_object *obj; if (!ring->private) return; - obj = pc->obj; + obj = ring->private; ring_destroy_object(obj); - kfree(pc); ring->private = NULL; } @@ -599,9 +567,9 @@ static int pc_render_add_request(struct intel_ring_buffer *ring, u32 *result) { + struct drm_i915_gem_object *obj = ring->private; u32 seqno = i915_gem_next_request_seqno(ring); - struct pipe_control *pc = ring->private; - u32 scratch_addr = pc->gtt_offset + 128; + u32 scratch_addr = obj->gtt_offset + 128; int ret; /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently @@ -619,7 +587,7 @@ pc_render_add_request(struct intel_ring_buffer *ring, intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_WRITE_FLUSH | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); - intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); + intel_ring_emit(ring, obj->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); intel_ring_emit(ring, seqno); intel_ring_emit(ring, 0); PIPE_CONTROL_FLUSH(ring, scratch_addr); @@ -638,7 +606,7 @@ pc_render_add_request(struct intel_ring_buffer *ring, PIPE_CONTROL_WRITE_FLUSH | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_NOTIFY); - intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); + intel_ring_emit(ring, obj->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); intel_ring_emit(ring, seqno); intel_ring_emit(ring, 0); intel_ring_advance(ring); @@ -669,8 +637,8 @@ ring_get_seqno(struct intel_ring_buffer *ring) static u32 pc_render_get_seqno(struct intel_ring_buffer *ring) { - struct pipe_control *pc = ring->private; - return pc->cpu_page[0]; + struct drm_i915_gem_object *obj = ring->private; + return ((volatile u32 *)obj->cpu_map)[0]; } static bool