From patchwork Mon Jul 16 18:25:20 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 1201441 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 19BE440071 for ; Mon, 16 Jul 2012 18:26:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DEEB19F753 for ; Mon, 16 Jul 2012 11:26:33 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id F3BFF9E88B for ; Mon, 16 Jul 2012 11:26:18 -0700 (PDT) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.66.37; Received: from arrandale.alporthouse.com (unverified [78.156.66.37]) by fireflyinternet.com (Firefly Internet SMTP) with ESMTP id 118347978-1500050 for multiple; Mon, 16 Jul 2012 19:26:08 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Mon, 16 Jul 2012 19:25:20 +0100 Message-Id: <1342463121-20842-1-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 1.7.10.4 X-Originating-IP: 78.156.66.37 Subject: [Intel-gfx] [PATCH 1/2] Add bare-metal interface to adjust cacheing (i.e. snoop status) of a bo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Signed-off-by: Chris Wilson --- lib/drmtest.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++ lib/drmtest.h | 3 +++ 2 files changed, 55 insertions(+) diff --git a/lib/drmtest.c b/lib/drmtest.c index 871c1d0..66f2887 100644 --- a/lib/drmtest.c +++ b/lib/drmtest.c @@ -252,6 +252,58 @@ void gem_set_tiling(int fd, uint32_t handle, int tiling, int stride) assert(st.tiling_mode == tiling); } +struct local_drm_i915_gem_cacheing { + uint32_t handle; + uint32_t cacheing; +}; + +#define LOCAL_DRM_I915_GEM_SET_CACHEING 0x2f +#define LOCAL_DRM_I915_GEM_GET_CACHEING 0x30 +#define LOCAL_DRM_IOCTL_I915_GEM_SET_CACHEING \ + DRM_IOW(DRM_COMMAND_BASE + LOCAL_DRM_I915_GEM_SET_CACHEING, struct local_drm_i915_gem_cacheing) +#define LOCAL_DRM_IOCTL_I915_GEM_GET_CACHEING \ + DRM_IOWR(DRM_COMMAND_BASE + LOCAL_DRM_I915_GEM_GET_CACHEING, struct local_drm_i915_gem_cacheing) + +int gem_has_cacheing(int fd) +{ + struct local_drm_i915_gem_cacheing arg; + int ret; + + arg.handle = gem_create(fd, 4096); + if (arg.handle == 0) + return 0; + + arg.cacheing = 0; + ret = ioctl(fd, LOCAL_DRM_IOCTL_I915_GEM_SET_CACHEING, &arg); + gem_close(fd, arg.handle); + + return ret == 0; +} + +void gem_set_cacheing(int fd, uint32_t handle, int cacheing) +{ + struct local_drm_i915_gem_cacheing arg; + int ret; + + arg.handle = handle; + arg.cacheing = cacheing; + ret = ioctl(fd, LOCAL_DRM_IOCTL_I915_GEM_SET_CACHEING, &arg); + assert(ret == 0); +} + +int gem_get_cacheing(int fd, uint32_t handle) +{ + struct local_drm_i915_gem_cacheing arg; + int ret; + + arg.handle = handle; + arg.cacheing = 0; + ret = ioctl(fd, LOCAL_DRM_IOCTL_I915_GEM_GET_CACHEING, &arg); + assert(ret == 0); + + return arg.cacheing; +} + void gem_close(int fd, uint32_t handle) { struct drm_gem_close close_bo; diff --git a/lib/drmtest.h b/lib/drmtest.h index 4021104..0208559 100644 --- a/lib/drmtest.h +++ b/lib/drmtest.h @@ -45,6 +45,9 @@ void gem_quiescent_gpu(int fd); /* ioctl wrappers and similar stuff for bare metal testing */ void gem_set_tiling(int fd, uint32_t handle, int tiling, int stride); +int gem_has_cacheing(int fd); +void gem_set_cacheing(int fd, uint32_t handle, int cacheing); +int gem_get_cacheing(int fd, uint32_t handle); void gem_close(int fd, uint32_t handle); void gem_write(int fd, uint32_t handle, uint32_t offset, const void *buf, uint32_t size); void gem_read(int fd, uint32_t handle, uint32_t offset, void *buf, uint32_t size);