From patchwork Thu Jul 19 20:00:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Olivier Galibert X-Patchwork-Id: 1218281 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 2C8E2DF25A for ; Thu, 19 Jul 2012 20:04:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0A46DA0FE7 for ; Thu, 19 Jul 2012 13:04:18 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from sasl.smtp.pobox.com (a-pb-sasl-sd.pobox.com [74.115.168.62]) by gabe.freedesktop.org (Postfix) with ESMTP id 094B59F065; Thu, 19 Jul 2012 12:59:59 -0700 (PDT) Received: from sasl.smtp.pobox.com (unknown [127.0.0.1]) by b-pb-sasl-sd.pobox.com (Postfix) with ESMTP id 864E7B8DA; Thu, 19 Jul 2012 15:59:59 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references; s=sasl; bh=F/x0 vLn8Z8ccynTCvCZh3sw66yA=; b=EEAg1avctygZmQUZNnHQ3dKz3j8zof0VJL1M N7nolBUBy5xZFjtbA6NGnwMGJYsEARiImhR5gZdn9bW/nAhlOsYkPanjY2ltJnzP NStwjNDP3LOn3E76mkgjjsE62OL7BkNqU8OyB7IKeRxEzCtkTXzYp/kPRbEoMDTU tyhhXss= DomainKey-Signature: a=rsa-sha1; c=nofws; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references; q=dns; s=sasl; b= rGnT2IqLA03Es0jW38T3Iam7e4XoXHw0DRZY6BppozRBcaO9DbZ14N/3yUE007Gi D5fRtjbsFqqWAfIy5XlVrc3sauD5Cc1jmW132OmGAMUuFq1uZG4AoZWnuDN+9xIg Nu1KtCHqCuffovY9pAVd09WGRzegI/NMVmTQSMyFcUU= Received: from b-pb-sasl-sd. (unknown [127.0.0.1]) by b-pb-sasl-sd.pobox.com (Postfix) with ESMTP id 78B58B8D9; Thu, 19 Jul 2012 15:59:59 -0400 (EDT) Received: from localhost.localdomain (unknown [82.234.121.82]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by b-pb-sasl-sd.pobox.com (Postfix) with ESMTPSA id 34775B8D8; Thu, 19 Jul 2012 15:59:57 -0400 (EDT) From: Olivier Galibert To: intel-gfx@lists.freedesktop.org, mesa-dev@lists.freedesktop.org Date: Thu, 19 Jul 2012 22:00:16 +0200 Message-Id: <1342728024-15055-2-git-send-email-galibert@pobox.com> X-Mailer: git-send-email 1.7.10.280.gaa39 In-Reply-To: <1342728024-15055-1-git-send-email-galibert@pobox.com> References: <1342728024-15055-1-git-send-email-galibert@pobox.com> X-Pobox-Relay-ID: 51801E60-D1DC-11E1-AEF3-126B87E41631-92059326!b-pb-sasl-sd.pobox.com Cc: Olivier Galibert Subject: [Intel-gfx] [PATCH 1/9] intel gen4-5: fix the vue view in the fs. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org In some cases the fragment shader view of the vue registers was out of sync with the builder. This fixes it. Signed-off-by: Olivier Galibert Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/i965/brw_fs.cpp | 9 ++++++++- src/mesa/drivers/dri/i965/brw_wm_pass2.c | 10 +++++++++- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index b3b25cc..3f98137 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -972,8 +972,15 @@ fs_visitor::calculate_urb_setup() if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) { int fp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i); + /* The back color slot is skipped when the front color is + * also written to. In addition, some slots can be + * written in the vertex shader and not read in the + * fragment shader. So the register number must always be + * incremented, mapped or not. + */ if (fp_index >= 0) - urb_setup[fp_index] = urb_next++; + urb_setup[fp_index] = urb_next; + urb_next++; } } diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c index 27c0a94..eacf7c0 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c +++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c @@ -97,8 +97,16 @@ static void init_registers( struct brw_wm_compile *c ) int fp_index = _mesa_vert_result_to_frag_attrib(j); nr_interp_regs++; + + /* The back color slot is skipped when the front color is + * also written to. In addition, some slots can be + * written in the vertex shader and not read in the + * fragment shader. So the register number must always be + * incremented, mapped or not. + */ if (fp_index >= 0) - prealloc_reg(c, &c->payload.input_interp[fp_index], i++); + prealloc_reg(c, &c->payload.input_interp[fp_index], i); + i++; } } assert(nr_interp_regs >= 1);