| Message ID | 1343244729-12867-1-git-send-email-daniel.vetter@ffwll.ch (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, 25 Jul 2012 21:32:09 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote: > The power docs say that when the gt leaves rc6, it is in the lowest > frequency and only about 25 usec later will switch to the frequency > selected in GEN6_RPNSWREQ. If the downclock limit expires in that > window and the down limit is set to the lowest possible frequency, the > hw will not send the down interrupt. Which leads to a too high gpu > clock and wasted power. > > Chris Wilson already worked on this with > > commit 7b9e0ae6da0a7eaf2680a1a788f08df123724f3b > Author: Chris Wilson <chris@chris-wilson.co.uk> > Date: Sat Apr 28 08:56:39 2012 +0100 > > drm/i915: Always update RPS interrupts thresholds along with > frequency > > but got the logic inverted: The current code set the down limit as > long as we haven't reached it. Instead of only once with reached the > lowest frequency. Yup, that's different to the opposite of what I thought I was writing to comply with the guide. :( Note you also have to fix up intel_sanitize_pm(). -Chris
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d0ce2a5..c2a7c9f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2275,13 +2275,18 @@ void gen6_set_rps(struct drm_device *dev, u8 val) limits = 0; if (val >= dev_priv->max_delay) val = dev_priv->max_delay; - else - limits |= dev_priv->max_delay << 24; - - if (val <= dev_priv->min_delay) + limits |= dev_priv->max_delay << 24; + + /* Only set the down limit when we've reached the lowest level to avoid + * getting more interrupts, otherwise leave this clear. This prevents a + * race in the hw when coming out of rc6: There's a tiny window where + * the hw runs at the minimal clock before selecting the desired + * frequency, if the down threshold expires in that window we will not + * receive a down interrupt. */ + if (val <= dev_priv->min_delay) { val = dev_priv->min_delay; - else limits |= dev_priv->min_delay << 16; + } if (val == dev_priv->cur_delay) return;
The power docs say that when the gt leaves rc6, it is in the lowest frequency and only about 25 usec later will switch to the frequency selected in GEN6_RPNSWREQ. If the downclock limit expires in that window and the down limit is set to the lowest possible frequency, the hw will not send the down interrupt. Which leads to a too high gpu clock and wasted power. Chris Wilson already worked on this with commit 7b9e0ae6da0a7eaf2680a1a788f08df123724f3b Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Sat Apr 28 08:56:39 2012 +0100 drm/i915: Always update RPS interrupts thresholds along with frequency but got the logic inverted: The current code set the down limit as long as we haven't reached it. Instead of only once with reached the lowest frequency. Note that we can't always set the downclock limit to 0, because otherwise the hw will keep on bugging us with downclock request irqs once the lowest level is reached. For similar reasons also always set the upclock limit, otherwise the hw might poke us again with interrupts. Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-)