From patchwork Tue Jul 31 02:47:02 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wang Xingchao X-Patchwork-Id: 1256951 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 21546DF24C for ; Tue, 31 Jul 2012 03:00:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9CD1A9F598 for ; Mon, 30 Jul 2012 20:00:00 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 64AE39EB35 for ; Mon, 30 Jul 2012 19:58:55 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 30 Jul 2012 19:58:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.67,351,1309762800"; d="scan'208";a="179583530" Received: from wxc-intel.bj.intel.com ([10.238.145.98]) by orsmga002.jf.intel.com with ESMTP; 30 Jul 2012 19:58:53 -0700 From: Wang Xingchao To: intel-gfx@lists.freedesktop.org Date: Tue, 31 Jul 2012 10:47:02 +0800 Message-Id: <1343702825-15439-2-git-send-email-xingchao.wang@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343702825-15439-1-git-send-email-xingchao.wang@intel.com> References: <1343702825-15439-1-git-send-email-xingchao.wang@intel.com> Cc: paulo.r.zanoni@intel.com Subject: [Intel-gfx] [PATCH V2 1/4] drm/i915: HSW audio registers definition X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Add hsw audio registers definition Signed-off-by: Wang Xingchao --- drivers/gpu/drm/i915/i915_reg.h | 46 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1310caa..00b0182 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4277,6 +4277,52 @@ #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) #define AUD_CONFIG_DISABLE_NCTS (1 << 3) +/* HSW Audio */ +#define HSW_AUD_CONFIG_A 0x65000 /*Audio Configuration Transcoder A*/ +#define HSW_AUD_CONFIG_B 0x65100 /*Audio Configuration Transcoder B*/ +#define HSW_AUD_CFG(pipe) _PIPE(pipe, \ + HSW_AUD_CONFIG_A, \ + HSW_AUD_CONFIG_B) +#define HSW_AUD_MISC_CTRL_A 0x65010 /*Audio Misc Control Convert 1*/ +#define HSW_AUD_MISC_CTRL_B 0x65110 /*Audio Misc Control Convert 2*/ +#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \ + HSW_AUD_MISC_CTRL_A, \ + HSW_AUD_MISC_CTRL_B) + +#define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /*Audio DIP and ELD Control State Transcoder A*/ +#define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /*Audio DIP and ELD Control State Transcoder B*/ +#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \ + HSW_AUD_DIP_ELD_CTRL_ST_A, \ + HSW_AUD_DIP_ELD_CTRL_ST_B) + +#define HSW_AUD_PIPE_CONV_CFG 0x6507c /*Audio pipe and converter configs*/ +#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /*Audio ELD and CP Ready Status*/ +#define AUDIO_INACTIVE_C (1<<11) +#define AUDIO_INACTIVE_B (1<<7) +#define AUDIO_INACTIVE_A (1<<3) +#define AUDIO_OUTPUT_ENABLE_AB (1<<2) +#define AUDIO_OUTPUT_ENABLE_BC (1<<6) +#define AUDIO_OUTPUT_ENABLE_CD (1<<10) +#define AUDIO_ELD_VALID_AB (1<<0) +#define AUDIO_ELD_VALID_BC (1<<4) +#define AUDIO_ELD_VALID_CD (1<<8) +#define AUDIO_CP_READY_AB (1<<1) +#define AUDIO_CP_READY_BC (1<<5) +#define AUDIO_CP_READY_CD (1<<9) + +/* Audio Digital Converter*/ +#define HSW_AUD_DIG_CNVT_1 0x65080 /*Audio Converter 1*/ +#define HSW_AUD_DIG_CNVT_2 0x65180 /*Audio Converter 1*/ +#define HSW_AUD_DIG_CNVT_3 0x65280 /*Audio Converter 1*/ + +#define HSW_AUD_EDID_DATA 0x65050 + +#define TRANS_CONF_A 0xf0008 +#define AUD_PB_UNSL_DEV_CP 0x65fb0 +#define AUD_PC_UNSL_DEV_CP 0x65fb4 +#define AUD_PD_UNSL_DEV_CP 0x65fb8 + + /* HSW Power Wells */ #define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */ #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */