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[libdrm] intel: add more Haswell PCI IDs

Message ID 1344289615-5109-1-git-send-email-przanoni@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Paulo Zanoni Aug. 6, 2012, 9:46 p.m. UTC
From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 intel/intel_chipset.h | 68 ++++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 65 insertions(+), 3 deletions(-)

Comments

Rodrigo Vivi Aug. 6, 2012, 10:20 p.m. UTC | #1
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Mon, Aug 6, 2012 at 6:46 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  intel/intel_chipset.h | 68 ++++++++++++++++++++++++++++++++++++++++++++++++---
>  1 file changed, 65 insertions(+), 3 deletions(-)
>
> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> index 9c1abc8..b73fa0f 100644
> --- a/intel/intel_chipset.h
> +++ b/intel/intel_chipset.h
> @@ -48,9 +48,40 @@
>
>  #define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
>  #define PCI_CHIP_HASWELL_GT2            0x0412
> +#define PCI_CHIP_HASWELL_GT2_PLUS       0x0422
>  #define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */
>  #define PCI_CHIP_HASWELL_M_GT2          0x0416
> -#define PCI_CHIP_HASWELL_M_ULT_GT2      0x0A16 /* Mobile ULT */
> +#define PCI_CHIP_HASWELL_M_GT2_PLUS     0x0426
> +#define PCI_CHIP_HASWELL_S_GT1          0x040A /* Server */
> +#define PCI_CHIP_HASWELL_S_GT2          0x041A
> +#define PCI_CHIP_HASWELL_S_GT2_PLUS     0x042A
> +#define PCI_CHIP_HASWELL_SDV_GT1        0x0C02 /* Desktop */
> +#define PCI_CHIP_HASWELL_SDV_GT2        0x0C12
> +#define PCI_CHIP_HASWELL_SDV_GT2_PLUS   0x0C22
> +#define PCI_CHIP_HASWELL_SDV_M_GT1      0x0C06 /* Mobile */
> +#define PCI_CHIP_HASWELL_SDV_M_GT2      0x0C16
> +#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
> +#define PCI_CHIP_HASWELL_SDV_S_GT1      0x0C0A /* Server */
> +#define PCI_CHIP_HASWELL_SDV_S_GT2      0x0C1A
> +#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
> +#define PCI_CHIP_HASWELL_ULT_GT1        0x0A02 /* Desktop */
> +#define PCI_CHIP_HASWELL_ULT_GT2        0x0A12
> +#define PCI_CHIP_HASWELL_ULT_GT2_PLUS   0x0A22
> +#define PCI_CHIP_HASWELL_ULT_M_GT1      0x0A06 /* Mobile */
> +#define PCI_CHIP_HASWELL_ULT_M_GT2      0x0A16
> +#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
> +#define PCI_CHIP_HASWELL_ULT_S_GT1      0x0A0A /* Server */
> +#define PCI_CHIP_HASWELL_ULT_S_GT2      0x0A1A
> +#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
> +#define PCI_CHIP_HASWELL_CRW_GT1        0x0D12 /* Desktop */
> +#define PCI_CHIP_HASWELL_CRW_GT2        0x0D22
> +#define PCI_CHIP_HASWELL_CRW_GT2_PLUS   0x0D32
> +#define PCI_CHIP_HASWELL_CRW_M_GT1      0x0D16 /* Mobile */
> +#define PCI_CHIP_HASWELL_CRW_M_GT2      0x0D26
> +#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
> +#define PCI_CHIP_HASWELL_CRW_S_GT1      0x0D1A /* Server */
> +#define PCI_CHIP_HASWELL_CRW_S_GT2      0x0D2A
> +#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
>
>  #define IS_830(dev) (dev == 0x3577)
>  #define IS_845(dev) (dev == 0x2562)
> @@ -133,10 +164,41 @@
>                                  dev == PCI_CHIP_IVYBRIDGE_S_GT2)
>
>  #define IS_HSW_GT1(devid)       (devid == PCI_CHIP_HASWELL_GT1 || \
> -                                 devid == PCI_CHIP_HASWELL_M_GT1)
> +                                devid == PCI_CHIP_HASWELL_M_GT1 || \
> +                                devid == PCI_CHIP_HASWELL_S_GT1 || \
> +                                devid == PCI_CHIP_HASWELL_SDV_GT1 || \
> +                                devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
> +                                devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
> +                                devid == PCI_CHIP_HASWELL_ULT_GT1 || \
> +                                devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
> +                                devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
> +                                devid == PCI_CHIP_HASWELL_CRW_GT1 || \
> +                                devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
> +                                devid == PCI_CHIP_HASWELL_CRW_S_GT1)
>  #define IS_HSW_GT2(devid)       (devid == PCI_CHIP_HASWELL_GT2 || \
>                                   devid == PCI_CHIP_HASWELL_M_GT2 || \
> -                                 devid == PCI_CHIP_HASWELL_M_ULT_GT2)
> +                                devid == PCI_CHIP_HASWELL_S_GT2 || \
> +                                devid == PCI_CHIP_HASWELL_SDV_GT2 || \
> +                                devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \
> +                                devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \
> +                                devid == PCI_CHIP_HASWELL_ULT_GT2 || \
> +                                devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \
> +                                devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
> +                                devid == PCI_CHIP_HASWELL_CRW_GT2 || \
> +                                devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
> +                                devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
> +                                devid == PCI_CHIP_HASWELL_GT2_PLUS || \
> +                                devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \
> +                                devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \
> +                                devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
> +                                devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
> +                                devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
> +                                devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
> +                                devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
> +                                devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
> +                                devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
> +                                devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
> +                                devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
>
>  #define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
>                                   IS_HSW_GT2(devid))
> --
> 1.7.11.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 9c1abc8..b73fa0f 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -48,9 +48,40 @@ 
 
 #define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
 #define PCI_CHIP_HASWELL_GT2            0x0412
+#define PCI_CHIP_HASWELL_GT2_PLUS       0x0422
 #define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */
 #define PCI_CHIP_HASWELL_M_GT2          0x0416
-#define PCI_CHIP_HASWELL_M_ULT_GT2      0x0A16 /* Mobile ULT */
+#define PCI_CHIP_HASWELL_M_GT2_PLUS     0x0426
+#define PCI_CHIP_HASWELL_S_GT1          0x040A /* Server */
+#define PCI_CHIP_HASWELL_S_GT2          0x041A
+#define PCI_CHIP_HASWELL_S_GT2_PLUS     0x042A
+#define PCI_CHIP_HASWELL_SDV_GT1        0x0C02 /* Desktop */
+#define PCI_CHIP_HASWELL_SDV_GT2        0x0C12
+#define PCI_CHIP_HASWELL_SDV_GT2_PLUS   0x0C22
+#define PCI_CHIP_HASWELL_SDV_M_GT1      0x0C06 /* Mobile */
+#define PCI_CHIP_HASWELL_SDV_M_GT2      0x0C16
+#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
+#define PCI_CHIP_HASWELL_SDV_S_GT1      0x0C0A /* Server */
+#define PCI_CHIP_HASWELL_SDV_S_GT2      0x0C1A
+#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
+#define PCI_CHIP_HASWELL_ULT_GT1        0x0A02 /* Desktop */
+#define PCI_CHIP_HASWELL_ULT_GT2        0x0A12
+#define PCI_CHIP_HASWELL_ULT_GT2_PLUS   0x0A22
+#define PCI_CHIP_HASWELL_ULT_M_GT1      0x0A06 /* Mobile */
+#define PCI_CHIP_HASWELL_ULT_M_GT2      0x0A16
+#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
+#define PCI_CHIP_HASWELL_ULT_S_GT1      0x0A0A /* Server */
+#define PCI_CHIP_HASWELL_ULT_S_GT2      0x0A1A
+#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
+#define PCI_CHIP_HASWELL_CRW_GT1        0x0D12 /* Desktop */
+#define PCI_CHIP_HASWELL_CRW_GT2        0x0D22
+#define PCI_CHIP_HASWELL_CRW_GT2_PLUS   0x0D32
+#define PCI_CHIP_HASWELL_CRW_M_GT1      0x0D16 /* Mobile */
+#define PCI_CHIP_HASWELL_CRW_M_GT2      0x0D26
+#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
+#define PCI_CHIP_HASWELL_CRW_S_GT1      0x0D1A /* Server */
+#define PCI_CHIP_HASWELL_CRW_S_GT2      0x0D2A
+#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
 
 #define IS_830(dev) (dev == 0x3577)
 #define IS_845(dev) (dev == 0x2562)
@@ -133,10 +164,41 @@ 
 				 dev == PCI_CHIP_IVYBRIDGE_S_GT2)
 
 #define IS_HSW_GT1(devid)       (devid == PCI_CHIP_HASWELL_GT1 || \
-                                 devid == PCI_CHIP_HASWELL_M_GT1)
+				 devid == PCI_CHIP_HASWELL_M_GT1 || \
+				 devid == PCI_CHIP_HASWELL_S_GT1 || \
+				 devid == PCI_CHIP_HASWELL_SDV_GT1 || \
+				 devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
+				 devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
+				 devid == PCI_CHIP_HASWELL_ULT_GT1 || \
+				 devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
+				 devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
+				 devid == PCI_CHIP_HASWELL_CRW_GT1 || \
+				 devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
+				 devid == PCI_CHIP_HASWELL_CRW_S_GT1)
 #define IS_HSW_GT2(devid)       (devid == PCI_CHIP_HASWELL_GT2 || \
                                  devid == PCI_CHIP_HASWELL_M_GT2 || \
-                                 devid == PCI_CHIP_HASWELL_M_ULT_GT2)
+				 devid == PCI_CHIP_HASWELL_S_GT2 || \
+				 devid == PCI_CHIP_HASWELL_SDV_GT2 || \
+				 devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \
+				 devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \
+				 devid == PCI_CHIP_HASWELL_ULT_GT2 || \
+				 devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \
+				 devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
+				 devid == PCI_CHIP_HASWELL_CRW_GT2 || \
+				 devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
+				 devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
+				 devid == PCI_CHIP_HASWELL_GT2_PLUS || \
+				 devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \
+				 devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \
+				 devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
+				 devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
+				 devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
+				 devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
+				 devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
+				 devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
+				 devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
+				 devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
+				 devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
 
 #define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
                                  IS_HSW_GT2(devid))