diff mbox

[V2,2/2] intel_audio_dump: add Haswell audio dump support

Message ID 1344329570-17939-3-git-send-email-xingchao.wang@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Wang Xingchao Aug. 7, 2012, 8:52 a.m. UTC 
Add Haswell audio registers definition and dump support.

Signed-off-by: Wang Xingchao <xingchao.wang@intel.com>
---
 tools/intel_audio_dump.c |  582 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 582 insertions(+)

Comments

Fengguang Wu Aug. 15, 2012, 8 a.m. UTC | #1 
Xingchao,

Have you tested the patch in haswell as well as in older hardwares?
In general it would be better if you have run this tool for some time
on several hardwares -- that's the best way to smooth out possible bugs.

> +/*Haswell registers*/

Please fix the style to (ditto for lots of other comments)

> +/* Haswell registers */

Thanks,
Fengguang
Wang Xingchao Aug. 15, 2012, 8:05 a.m. UTC | #2 
Hi Fengguang,

> -----Original Message-----
> From: Wu, Fengguang
> Sent: Wednesday, August 15, 2012 4:01 PM
> To: Wang, Xingchao
> Cc: intel-gfx@lists.freedesktop.org; daniel@ffwll.ch; Fu, Michael;
> zhenyuw@linux.intel.com
> Subject: Re: [PATCH V2 2/2] intel_audio_dump: add Haswell audio dump
> support
> 
> Xingchao,
> 
> Have you tested the patch in haswell as well as in older hardwares?

I tested this patch on Haswell platform platform several times. It helped me much during debug.
And this patch has no impact for older hardwares(such as ivybridge), as it only works for Haswell.

> In general it would be better if you have run this tool for some time on several
> hardwares -- that's the best way to smooth out possible bugs.
> 
> > +/*Haswell registers*/

> 
> Please fix the style to (ditto for lots of other comments)
> 
> > +/* Haswell registers */

Thanks, will clean up that.

--xingchao
diff mbox

Patch

diff --git a/tools/intel_audio_dump.c b/tools/intel_audio_dump.c
index 8a0f6ee..5ee9372 100644
--- a/tools/intel_audio_dump.c
+++ b/tools/intel_audio_dump.c
@@ -94,6 +94,11 @@  static const char *dip_port[] = {
 	[3] = "Digital Port D",
 };
 
+static const char *dip_type[] = {
+        [0] = "Audio DIP Disabled",
+        [1] = "Audio DIP Enabled",
+};
+
 static const char *dip_index[] = {
 	[0] = "Audio DIP",
 	[1] = "ACP DIP",
@@ -134,6 +139,17 @@  static const char *trans_to_port_sel[] = {
 	[7] = "reserved",
 };
 
+static const char *ddi_mode[] = {
+	[0] = "HDMI mode",
+	[1] = "DVI mode",
+	[2] = "DP SST mode",
+	[3] = "DP MST mode",
+	[4] = "DP FDI mode",
+	[5] = "reserved",
+	[6] = "reserved",
+	[7] = "reserved",
+};
+
 static const char *transcoder_select[] = {
 	[0] = "Transcoder A",
 	[1] = "Transcoder B",
@@ -1354,6 +1370,567 @@  static void dump_cpt(void)
 
 }
 
+#undef AUD_CONFIG_A
+#undef AUD_MISC_CTRL_A
+#undef AUD_VID_DID
+#undef AUD_RID
+#undef AUD_CTS_ENABLE_A
+#undef AUD_PWRST
+#undef AUD_HDMIW_HDMIEDID_A
+#undef AUD_HDMIW_INFOFR_A
+#undef AUD_PORT_EN_HD_CFG
+#undef AUD_OUT_DIG_CNVT_A
+#undef AUD_OUT_STR_DESC_A
+#undef AUD_OUT_CH_STR
+#undef AUD_PINW_CONNLNG_LIST
+#undef AUD_CNTL_ST_A
+#undef AUD_HDMIW_STATUS
+#undef AUD_CONFIG_B
+#undef AUD_MISC_CTRL_B
+#undef AUD_CTS_ENABLE_B
+#undef AUD_HDMIW_HDMIEDID_B
+#undef AUD_HDMIW_INFOFR_B
+#undef AUD_OUT_DIG_CNVT_B
+#undef AUD_OUT_STR_DESC_B
+#undef AUD_CNTL_ST_B
+#undef AUD_CONFIG_C
+#undef AUD_MISC_CTRL_C
+#undef AUD_CTS_ENABLE_C
+#undef AUD_HDMIW_HDMIEDID_C
+#undef AUD_HDMIW_INFOFR_C
+#undef AUD_OUT_DIG_CNVT_C
+#undef AUD_OUT_STR_DESC_C
+
+#undef VIDEO_DIP_CTL_A
+#undef VIDEO_DIP_CTL_B
+#undef VIDEO_DIP_CTL_C
+#undef VIDEO_DIP_CTL_D
+#undef VIDEO_DIP_DATA
+
+/*Haswell registers*/
+
+/*DisplayPort Transport Control*/
+#define DP_TP_CTL_A	    0x64040
+#define DP_TP_CTL_B	    0x64140
+#define DP_TP_CTL_C	    0x64240
+#define DP_TP_CTL_D	    0x64340
+#define DP_TP_CTL_E	    0x64440
+
+/*DisplayPort Transport Status*/
+#define DP_TP_ST_A          0x64044
+#define DP_TP_ST_B          0x64144
+#define DP_TP_ST_C          0x64244
+#define DP_TP_ST_D          0x64344
+#define DP_TP_ST_E          0x64444
+
+/*Transcoder configuration*/
+#define TRANS_CONF_A	    0xF0008
+#define TRANS_CONF_B	    0xF1008
+#define TRANS_CONF_C	    0xF2008
+
+/*DDI Buffer Control*/
+#define DDI_BUF_CTL_A	      0x64000
+#define DDI_BUF_CTL_B	      0x64100
+#define DDI_BUF_CTL_C	      0x64200
+#define DDI_BUF_CTL_D	      0x64300
+#define DDI_BUF_CTL_E	      0x64400
+
+/*DDI Buffer Translation*/
+#define DDI_BUF_TRANS_A		0x64e00
+#define DDI_BUF_TRANS_B		0x64e60
+#define DDI_BUF_TRANS_C		0x64ec0
+#define DDI_BUF_TRANS_D		0x64f20
+#define DDI_BUF_TRANS_E		0x64f80
+
+/*DDI Aux Channel*/
+#define DDI_AUX_CHANNEL_CTRL	0x64010
+#define DDI_AUX_DATA		0x64014
+#define DDI_AUX_TST		0x64028
+
+/*DDI CRC Control*/
+#define DDI_CRC_CTL_A       0x64050
+#define DDI_CRC_CTL_B       0x64150
+#define DDI_CRC_CTL_C       0x64250
+#define DDI_CRC_CTL_D       0x64350
+#define DDI_CRC_CTL_E       0x64450
+
+/*Pipe DDI Function Control*/
+#define PIPE_DDI_FUNC_CTL_A   0x60400 
+#define PIPE_DDI_FUNC_CTL_B   0x61400 
+#define PIPE_DDI_FUNC_CTL_C   0x62400 
+#define PIPE_DDI_FUNC_CTL_EDP 0x6F400 
+
+/*Pipe Configuration*/
+#define PIPE_CONF_A		0x70008
+#define PIPE_CONF_B		0x71008
+#define PIPE_CONF_C		0x72008
+#define PIPE_CONF_EDP		0x7F008
+
+/*Audio registers*/
+#define AUD_CONFIG_A          0x65000
+#define AUD_MISC_CTRL_A       0x65010
+#define AUD_VID_DID           0x65020
+#define AUD_RID               0x65024
+#define AUD_CTS_ENABLE_A      0x65028
+#define AUD_PWRST             0x6504C
+#define AUD_HDMIW_HDMIEDID_A  0x65050
+#define AUD_HDMIW_INFOFR_A    0x65054
+#define AUD_PORT_EN_HD_CFG    0x6507C
+#define AUD_OUT_DIG_CNVT_A    0x65080
+#define AUD_OUT_STR_DESC_A    0x65084
+#define AUD_OUT_CHAN_MAP      0x65088
+#define AUD_PINW_CONNLNG_LIST_A 0x650A8
+#define AUD_PINW_CONNLNG_LIST_B 0x651A8
+#define AUD_PINW_CONNLNG_LIST_C 0x652A8
+#define AUD_PIPE_CONN_SEL_CTRL	0x650AC
+#define AUD_PIN_ELD_CP_VLD    0x650C0
+#define AUD_HDMIW_STATUS      0x650D4
+#define AUD_CONFIG_B          0x65100
+#define AUD_MISC_CTRL_B       0x65110
+#define AUD_CTS_ENABLE_B      0x65128
+#define AUD_HDMIW_HDMIEDID_B  0x65150
+#define AUD_HDMIW_INFOFR_B    0x65154
+#define AUD_OUT_DIG_CNVT_B    0x65180
+#define AUD_OUT_STR_DESC_B    0x65184
+#define AUD_CONFIG_C          0x65200
+#define AUD_MISC_CTRL_C       0x65210
+#define AUD_CTS_ENABLE_C      0x65228
+#define AUD_HDMIW_HDMIEDID_C  0x65250
+#define AUD_HDMIW_INFOFR_C    0x65254
+#define AUD_OUT_DIG_CNVT_C    0x65280
+#define AUD_OUT_STR_DESC_C    0x65284
+#define AUD_DIP_ELD_CTRL_ST_A	0x650b4
+#define AUD_DIP_ELD_CTRL_ST_B	0x651b4
+#define AUD_DIP_ELD_CTRL_ST_C	0x652b4
+
+/*Video DIP Control*/
+#define VIDEO_DIP_CTL_A		0x60200
+#define VIDEO_DIP_CTL_B		0x61200
+#define VIDEO_DIP_CTL_C		0x62200
+#define VIDEO_DIP_CTL_D		0x63200
+
+#define VIDEO_DIP_DATA		0x60220
+#define VIDEO_DIP_ECC		0x60240
+
+#define AUD_DP_DIP_STATUS	0x65f20
+
+
+static void dump_hsw(void)
+{
+    uint32_t dword;
+    int i;
+
+    /*HSW DDI Buffer*/
+    dump_reg(DDI_BUF_CTL_A,		"DDI Buffer Controler A");
+    dump_reg(DDI_BUF_CTL_B,		"DDI Buffer Controler B");
+    dump_reg(DDI_BUF_CTL_C,		"DDI Buffer Controler C");
+    dump_reg(DDI_BUF_CTL_D,		"DDI Buffer Controler D");
+    dump_reg(DDI_BUF_CTL_E,		"DDI Buffer Controler E");
+    
+    /*HSW Pipe Function*/
+    dump_reg(PIPE_CONF_A,		"PIPE Configuration A");
+    dump_reg(PIPE_CONF_B,		"PIPE Configuration B");
+    dump_reg(PIPE_CONF_C,		"PIPE Configuration C");
+    dump_reg(PIPE_CONF_EDP,		"PIPE Configuration EDP");
+
+    dump_reg(PIPE_DDI_FUNC_CTL_A,	"PIPE DDI Function Control A");
+    dump_reg(PIPE_DDI_FUNC_CTL_B,	"PIPE DDI Function Control B");
+    dump_reg(PIPE_DDI_FUNC_CTL_C,	"PIPE DDI Function Control C");
+    dump_reg(PIPE_DDI_FUNC_CTL_EDP,	"PIPE DDI Function Control EDP");
+   
+    /*HSW Display port*/
+    dump_reg(DP_TP_CTL_A,		"DisplayPort Transport A Control");
+    dump_reg(DP_TP_CTL_B,		"DisplayPort Transport B Control");
+    dump_reg(DP_TP_CTL_C,		"DisplayPort Transport C Control");
+    dump_reg(DP_TP_CTL_D,		"DisplayPort Transport D Control");
+    dump_reg(DP_TP_CTL_E,		"DisplayPort Transport E Control");
+
+    dump_reg(DP_TP_ST_A,		"DisplayPort Transport A Status");
+    dump_reg(DP_TP_ST_B,		"DisplayPort Transport B Status");
+    dump_reg(DP_TP_ST_C,		"DisplayPort Transport C Status");
+    dump_reg(DP_TP_ST_D,		"DisplayPort Transport D Status");
+    dump_reg(DP_TP_ST_E,		"DisplayPort Transport E Status");
+
+    /*HSW Transcoder A configuration*/
+    dump_reg(TRANS_CONF_A,		"Transcoder A Configuration");
+    dump_reg(TRANS_CONF_B,		"Transcoder B Configuration");
+    dump_reg(TRANS_CONF_C,		"Transcoder C Configuration");
+
+    /*HSW North Display Audio*/
+    dump_reg(AUD_CONFIG_A,		"Audio Configuration - Transcoder A");
+    dump_reg(AUD_CONFIG_B,		"Audio Configuration - Transcoder B");
+    dump_reg(AUD_CONFIG_C,		"Audio Configuration - Transcoder C");
+    dump_reg(AUD_MISC_CTRL_A,		"Audio MISC Control for Transcoder A");
+    dump_reg(AUD_MISC_CTRL_B,		"Audio MISC Control for Transcoder B");
+    dump_reg(AUD_MISC_CTRL_C,		"Audio MISC Control for Transcoder C");
+    dump_reg(AUD_VID_DID,		"Audio Vendor ID / Device ID");
+    dump_reg(AUD_RID,			"Audio Revision ID");
+    dump_reg(AUD_CTS_ENABLE_A,		"Audio CTS Programming Enable - Transcoder A");
+    dump_reg(AUD_CTS_ENABLE_B,		"Audio CTS Programming Enable - Transcoder B");
+    dump_reg(AUD_CTS_ENABLE_C,		"Audio CTS Programming Enable - Transcoder C");
+    dump_reg(AUD_PWRST,			"Audio Power State (Function Group, Convertor, Pin Widget)");
+    dump_reg(AUD_HDMIW_HDMIEDID_A,	"HDMI Data EDID Block - Transcoder A");
+    dump_reg(AUD_HDMIW_HDMIEDID_B,	"HDMI Data EDID Block - Transcoder B");
+    dump_reg(AUD_HDMIW_HDMIEDID_C,	"HDMI Data EDID Block - Transcoder C");
+    dump_reg(AUD_HDMIW_INFOFR_A,	"Audio Widget Data Island Packet - Transcoder A");
+    dump_reg(AUD_HDMIW_INFOFR_B,	"Audio Widget Data Island Packet - Transcoder B");
+    dump_reg(AUD_HDMIW_INFOFR_C,	"Audio Widget Data Island Packet - Transcoder C");
+
+    dump_reg(AUD_PORT_EN_HD_CFG,	"Audio Pipe and Convert Configs");
+    dump_reg(AUD_OUT_DIG_CNVT_A,	"Audio Digital Converter - Conv A");
+    dump_reg(AUD_OUT_DIG_CNVT_B,	"Audio Digital Converter - Conv B");
+    dump_reg(AUD_OUT_DIG_CNVT_C,	"Audio Digital Converter - Conv C");
+    dump_reg(AUD_OUT_CHAN_MAP,		"Audio Output Channel Mapping");
+    dump_reg(AUD_OUT_STR_DESC_A,	"Audio Stream Descriptor Format - Conv A");
+    dump_reg(AUD_OUT_STR_DESC_B,	"Audio Stream Descriptor Format - Conv B");
+    dump_reg(AUD_OUT_STR_DESC_C,	"Audio Stream Descriptor Format - Conv C");
+    dump_reg(AUD_PINW_CONNLNG_LIST_A,	"Audio Connection List entry and Length - Transcoder A");
+    dump_reg(AUD_PINW_CONNLNG_LIST_B,	"Audio Connection List entry and Length - Transcoder B");
+    dump_reg(AUD_PINW_CONNLNG_LIST_C,	"Audio Connection List entry and Length - Transcoder C");
+    dump_reg(AUD_PIPE_CONN_SEL_CTRL,	"Audio Pipe Connection Select Control");
+    dump_reg(AUD_DIP_ELD_CTRL_ST_A,	"Audio DIP and ELD control state - Transcoder A");
+    dump_reg(AUD_DIP_ELD_CTRL_ST_B,	"Audio DIP and ELD control state - Transcoder B");
+    dump_reg(AUD_DIP_ELD_CTRL_ST_C,	"Audio DIP and ELD control state - Transcoder C");
+    dump_reg(AUD_PIN_ELD_CP_VLD,	"audio pin eld valid status");
+    dump_reg(AUD_HDMIW_STATUS,		"Audio HDMI FIFO Status");
+
+    printf("\nDetails:\n\n");
+
+    dword = INREG(AUD_VID_DID);
+    printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
+    printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
+
+    dword = INREG(AUD_RID);
+    printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
+    printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
+    printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n",    BITS(dword, 15, 8));
+    printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n",    BITS(dword, 7, 0));
+
+    dword = INREG(AUD_DIP_ELD_CTRL_ST_A);
+    printf("Audio DIP and ELD control state for TranscoderA\n");
+    printf("Audio DIP port select\t\t\t\t\t[0x%lx] %s\n",
+		BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
+
+    printf("Audio DIP type enable status\t\t\t\t[0x%lx] %s\n",
+ 		BITS(dword, 24, 21), dip_type[BIT(dword, 21)]);
+
+    printf("DIP Buffer Index \t\t\t\t\t[0x%lx] %s\n",
+			BITS(dword, 20, 18), dip_index[BITS(dword, 20, 18)]);
+    printf("DIP_transmission_frequency\t\t\t\t[0x%lx] %s\n",
+					BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
+    printf("ELD_ACK\t\t\t\t\t\t\t%lu\n", BIT(dword, 4));
+    printf("ELD_buffer_size\t\t\t\t\t\t%lu\n", BITS(dword, 14, 10));
+
+    dword = INREG(AUD_DIP_ELD_CTRL_ST_B);
+    printf("Audio DIP and ELD control state for TranscoderB\n");
+    printf("Audio DIP port select\t\t\t\t\t[0x%lx] %s\n",
+		BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
+
+    printf("Audio DIP type enable status\t\t\t\t[0x%lx] %s\n",
+ 		BITS(dword, 24, 21), dip_type[BIT(dword, 21)]);
+
+    printf("DIP Buffer Index \t\t\t\t\t[0x%lx] %s\n",
+			BITS(dword, 20, 18), dip_index[BITS(dword, 20, 18)]);
+    printf("DIP_transmission_frequency\t\t\t\t[0x%lx] %s\n",
+					BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
+    printf("ELD_ACK\t\t\t\t\t\t\t%lu\n", BIT(dword, 4));
+    printf("ELD_buffer_size\t\t\t\t\t\t%lu\n", BITS(dword, 14, 10));
+
+    dword = INREG(AUD_DIP_ELD_CTRL_ST_C);
+    printf("Audio DIP and ELD control state for TranscoderC\n");
+    printf("Audio DIP port select\t\t\t\t\t[0x%lx] %s\n",
+		BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
+
+    printf("Audio DIP type enable status\t\t\t\t[0x%lx] %s\n",
+ 		BITS(dword, 24, 21), dip_type[BIT(dword, 21)]);
+
+    printf("DIP Buffer Index \t\t\t\t\t[0x%lx] %s\n",
+			BITS(dword, 20, 18), dip_index[BITS(dword, 20, 18)]);
+    printf("DIP_transmission_frequency\t\t\t\t[0x%lx] %s\n",
+					BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
+    printf("ELD_ACK\t\t\t\t\t\t\t%lu\n", BIT(dword, 4));
+    printf("ELD_buffer_size\t\t\t\t\t\t%lu\n", BITS(dword, 14, 10));
+ 
+    dword = INREG(DDI_BUF_CTL_A);
+    printf("DDI A Buffer control\n");
+    printf("DDI Buffer Enable\t\t\t\t\t%ld\n", BIT(dword, 31));
+    printf("DP port width\t\t\t\t\t\t[0x%lx] %s\n",
+		BITS(dword, 3, 1), dp_port_width[BITS(dword, 3, 1)]);
+    dword = INREG(DDI_BUF_CTL_B);
+    printf("DDI B Buffer control\n");
+    printf("DDI Buffer Enable\t\t\t\t\t%ld\n", BIT(dword, 31));
+    printf("DP port width\t\t\t\t\t\t[0x%lx] %s\n",
+			BITS(dword, 3, 1), dp_port_width[BITS(dword, 3, 1)]);
+    dword = INREG(DDI_BUF_CTL_C);
+    printf("DDI C Buffer control\n");
+    printf("DDI Buffer Enable\t\t\t\t\t%ld\n", BIT(dword, 31));
+    printf("DP port width\t\t\t\t\t\t[0x%lx] %s\n",
+			BITS(dword, 3, 1), dp_port_width[BITS(dword, 3, 1)]);
+    dword = INREG(DDI_BUF_CTL_D);
+    printf("DDI D Buffer control\n");
+    printf("DDI Buffer Enable\t\t\t\t\t%ld\n", BIT(dword, 31));
+    printf("DP port width\t\t\t\t\t\t[0x%lx] %s\n",
+			BITS(dword, 3, 1), dp_port_width[BITS(dword, 3, 1)]);
+    dword = INREG(DDI_BUF_CTL_E);
+    printf("DDI E Buffer control\n");
+    printf("DDI Buffer Enable\t\t\t\t\t%ld\n", BIT(dword, 31));
+    printf("DP port width\t\t\t\t\t\t[0x%lx] %s\n",
+			BITS(dword, 3, 1), dp_port_width[BITS(dword, 3, 1)]);
+
+    dword = INREG(PIPE_DDI_FUNC_CTL_A);
+    printf("Pipe A DDI Function Control\n");
+    printf("PIPE DDI Function Enable\t\t\t\t[0x%lx]\n", BIT(dword, 31));
+    printf("PIPE DDI selection\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 30, 28), 
+		trans_to_port_sel[BITS(dword, 30, 28)]);
+    printf("PIPE DDI Mode\t\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 26, 24), ddi_mode[BITS(dword, 26, 24)]);
+    printf("BITS per color\t\t\t\t\t\t[0x%lx]\n", BITS(dword, 22, 20));
+
+    dword = INREG(PIPE_DDI_FUNC_CTL_B);
+    printf("Pipe B DDI Function Control\n");
+    printf("PIPE DDI Function Enable\t\t\t\t[0x%lx]\n", BIT(dword, 31));
+    printf("PIPE DDI selection\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 30, 28), 
+		trans_to_port_sel[BITS(dword, 30, 28)]);
+    printf("PIPE DDI Mode \t\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 26, 24), ddi_mode[BITS(dword, 26, 24)]);
+    printf("BITS per color\t\t\t\t\t\t[0x%lx]\n", BITS(dword, 22, 20));
+
+    dword = INREG(PIPE_DDI_FUNC_CTL_C);
+    printf("Pipe C DDI Function Control\n");
+    printf("PIPE DDI Function Enable\t\t\t\t[0x%lx]\n", BIT(dword, 31));
+    printf("PIPE DDI selection\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 30, 28), 
+		trans_to_port_sel[BITS(dword, 30, 28)]);
+    printf("PIPE DDI Mode \t\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 26, 24), ddi_mode[BITS(dword, 26, 24)]);
+    printf("BITS per color\t\t\t\t\t\t[0x%lx]\n", BITS(dword, 22, 20));
+
+    dword = INREG(AUD_CONFIG_A);
+    printf("AUD_CONFIG_A  N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29),
+						n_index_value[BIT(dword, 29)]);
+    printf("AUD_CONFIG_A  N_programming_enable\t\t\t%lu\n", BIT(dword, 28));
+    printf("AUD_CONFIG_A  Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20));
+    printf("AUD_CONFIG_A  Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4));
+    printf("AUD_CONFIG_A  Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
+		    OPNAME(pixel_clock, BITS(dword, 19, 16)));
+    printf("AUD_CONFIG_A  Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3));
+    dword = INREG(AUD_CONFIG_B);
+    printf("AUD_CONFIG_B  N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29),
+						n_index_value[BIT(dword, 29)]);
+    printf("AUD_CONFIG_B  N_programming_enable\t\t\t%lu\n", BIT(dword, 28));
+    printf("AUD_CONFIG_B  Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20));
+    printf("AUD_CONFIG_B  Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4));
+    printf("AUD_CONFIG_B  Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
+		    OPNAME(pixel_clock, BITS(dword, 19, 16)));
+    printf("AUD_CONFIG_B  Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3));
+    dword = INREG(AUD_CONFIG_C);
+    printf("AUD_CONFIG_C  N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29),
+						n_index_value[BIT(dword, 29)]);
+    printf("AUD_CONFIG_C  N_programming_enable\t\t\t%lu\n", BIT(dword, 28));
+    printf("AUD_CONFIG_C  Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20));
+    printf("AUD_CONFIG_C  Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4));
+    printf("AUD_CONFIG_C  Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
+		    OPNAME(pixel_clock, BITS(dword, 19, 16)));
+    printf("AUD_CONFIG_C  Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3));
+
+    dword = INREG(AUD_CTS_ENABLE_A);
+    printf("AUD_CTS_ENABLE_A  Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
+    printf("AUD_CTS_ENABLE_A  CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
+    printf("AUD_CTS_ENABLE_A  CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
+    dword = INREG(AUD_CTS_ENABLE_B);
+    printf("AUD_CTS_ENABLE_B  Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
+    printf("AUD_CTS_ENABLE_B  CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
+    printf("AUD_CTS_ENABLE_B  CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
+    dword = INREG(AUD_CTS_ENABLE_C);
+    printf("AUD_CTS_ENABLE_C  Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
+    printf("AUD_CTS_ENABLE_C  CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
+    printf("AUD_CTS_ENABLE_C  CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
+
+    dword = INREG(AUD_MISC_CTRL_A);
+    printf("AUD_MISC_CTRL_A  Sample_Fabrication_EN_bit\t\t%lu\n",	BIT(dword, 2));
+    printf("AUD_MISC_CTRL_A  Sample_present_Disable\t\t\t%lu\n",	BIT(dword, 8));
+    printf("AUD_MISC_CTRL_A  Output_Delay\t\t\t\t%lu\n",		BITS(dword, 7, 4));
+    printf("AUD_MISC_CTRL_A  Pro_Allowed\t\t\t\t%lu\n",			BIT(dword, 1));
+    dword = INREG(AUD_MISC_CTRL_B);
+    printf("AUD_MISC_CTRL_B  Sample_Fabrication_EN_bit\t\t%lu\n",	BIT(dword, 2));
+    printf("AUD_MISC_CTRL_B  Sample_present_Disable\t\t\t%lu\n",	BIT(dword, 8));
+    printf("AUD_MISC_CTRL_B  Output_Delay\t\t\t\t%lu\n",		BITS(dword, 7, 4));
+    printf("AUD_MISC_CTRL_B  Pro_Allowed\t\t\t\t%lu\n",			BIT(dword, 1));
+    dword = INREG(AUD_MISC_CTRL_C);
+    printf("AUD_MISC_CTRL_C  Sample_Fabrication_EN_bit\t\t%lu\n",	BIT(dword, 2));
+    printf("AUD_MISC_CTRL_C  Sample_present_Disable\t\t\t%lu\n",	BIT(dword, 8));
+    printf("AUD_MISC_CTRL_C  Output_Delay\t\t\t\t%lu\n",		BITS(dword, 7, 4));
+    printf("AUD_MISC_CTRL_C  Pro_Allowed\t\t\t\t%lu\n",			BIT(dword, 1));
+
+    dword = INREG(AUD_PWRST);
+    printf("AUD_PWRST  Func_Grp_Dev_PwrSt_Curr                  \t%s\n", power_state[BITS(dword, 27, 26)]);
+    printf("AUD_PWRST  Func_Grp_Dev_PwrSt_Set                   \t%s\n", power_state[BITS(dword, 25, 24)]);
+    printf("AUD_PWRST  ConvertorA_Widget_Power_State_Current    \t%s\n", power_state[BITS(dword, 15, 14)]);
+    printf("AUD_PWRST  ConvertorA_Widget_Power_State_Requsted   \t%s\n", power_state[BITS(dword, 13, 12)]);
+    printf("AUD_PWRST  ConvertorB_Widget_Power_State_Current    \t%s\n", power_state[BITS(dword, 19, 18)]);
+    printf("AUD_PWRST  ConvertorB_Widget_Power_State_Requested  \t%s\n", power_state[BITS(dword, 17, 16)]);
+    printf("AUD_PWRST  ConvC_Widget_PwrSt_Curr                  \t%s\n", power_state[BITS(dword, 23, 22)]);
+    printf("AUD_PWRST  ConvC_Widget_PwrSt_Req                   \t%s\n", power_state[BITS(dword, 21, 20)]);
+    printf("AUD_PWRST  PinB_Widget_Power_State_Current          \t%s\n", power_state[BITS(dword,  3,  2)]);
+    printf("AUD_PWRST  PinB_Widget_Power_State_Set              \t%s\n", power_state[BITS(dword,  1,  0)]);
+    printf("AUD_PWRST  PinC_Widget_Power_State_Current          \t%s\n", power_state[BITS(dword,  7,  6)]);
+    printf("AUD_PWRST  PinC_Widget_Power_State_Set              \t%s\n", power_state[BITS(dword,  5,  4)]);
+    printf("AUD_PWRST  PinD_Widget_Power_State_Current          \t%s\n", power_state[BITS(dword, 11, 10)]);
+    printf("AUD_PWRST  PinD_Widget_Power_State_Set              \t%s\n", power_state[BITS(dword,  9,  8)]);
+
+    dword = INREG(AUD_PORT_EN_HD_CFG);
+    printf("AUD_PORT_EN_HD_CFG  Convertor_A_Digen\t\t\t%lu\n",	BIT(dword, 0));
+    printf("AUD_PORT_EN_HD_CFG  Convertor_B_Digen\t\t\t%lu\n",	BIT(dword, 1));
+    printf("AUD_PORT_EN_HD_CFG  Convertor_C_Digen\t\t\t%lu\n",	BIT(dword, 2));
+    printf("AUD_PORT_EN_HD_CFG  ConvertorA_Stream_ID\t\t%lu\n",	BITS(dword,  7, 4));
+    printf("AUD_PORT_EN_HD_CFG  ConvertorB_Stream_ID\t\t%lu\n",	BITS(dword, 11, 8));
+    printf("AUD_PORT_EN_HD_CFG  ConvertorC_Stream_ID\t\t%lu\n",	BITS(dword, 15, 12));
+    printf("AUD_PORT_EN_HD_CFG  Port_B_Out_Enable\t\t\t%lu\n",	BIT(dword, 16));
+    printf("AUD_PORT_EN_HD_CFG  Port_C_Out_Enable\t\t\t%lu\n",	BIT(dword, 17));
+    printf("AUD_PORT_EN_HD_CFG  Port_D_Out_Enable\t\t\t%lu\n",	BIT(dword, 18));
+    printf("AUD_PORT_EN_HD_CFG  Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 20));
+    printf("AUD_PORT_EN_HD_CFG  Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 21));
+    printf("AUD_PORT_EN_HD_CFG  Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 22));
+
+    dword = INREG(AUD_OUT_DIG_CNVT_A);
+    printf("AUD_OUT_DIG_CNVT_A  V\t\t\t\t\t%lu\n",		BIT(dword, 1));
+    printf("AUD_OUT_DIG_CNVT_A  VCFG\t\t\t\t%lu\n",		BIT(dword, 2));
+    printf("AUD_OUT_DIG_CNVT_A  PRE\t\t\t\t\t%lu\n",		BIT(dword, 3));
+    printf("AUD_OUT_DIG_CNVT_A  Copy\t\t\t\t%lu\n",		BIT(dword, 4));
+    printf("AUD_OUT_DIG_CNVT_A  NonAudio\t\t\t\t%lu\n",		BIT(dword, 5));
+    printf("AUD_OUT_DIG_CNVT_A  PRO\t\t\t\t\t%lu\n",		BIT(dword, 6));
+    printf("AUD_OUT_DIG_CNVT_A  Level\t\t\t\t%lu\n",		BIT(dword, 7));
+    printf("AUD_OUT_DIG_CNVT_A  Category_Code\t\t\t%lu\n",	BITS(dword, 14, 8));
+    printf("AUD_OUT_DIG_CNVT_A  Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
+    printf("AUD_OUT_DIG_CNVT_A  Stream_ID\t\t\t\t%lu\n",	BITS(dword, 23, 20));
+
+    dword = INREG(AUD_OUT_DIG_CNVT_B);
+    printf("AUD_OUT_DIG_CNVT_B  V\t\t\t\t\t%lu\n",		BIT(dword, 1));
+    printf("AUD_OUT_DIG_CNVT_B  VCFG\t\t\t\t%lu\n",		BIT(dword, 2));
+    printf("AUD_OUT_DIG_CNVT_B  PRE\t\t\t\t\t%lu\n",		BIT(dword, 3));
+    printf("AUD_OUT_DIG_CNVT_B  Copy\t\t\t\t%lu\n",		BIT(dword, 4));
+    printf("AUD_OUT_DIG_CNVT_B  NonAudio\t\t\t\t%lu\n",		BIT(dword, 5));
+    printf("AUD_OUT_DIG_CNVT_B  PRO\t\t\t\t\t%lu\n",		BIT(dword, 6));
+    printf("AUD_OUT_DIG_CNVT_B  Level\t\t\t\t%lu\n",		BIT(dword, 7));
+    printf("AUD_OUT_DIG_CNVT_B  Category_Code\t\t\t%lu\n",	BITS(dword, 14, 8));
+    printf("AUD_OUT_DIG_CNVT_B  Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
+    printf("AUD_OUT_DIG_CNVT_B  Stream_ID\t\t\t\t%lu\n",	BITS(dword, 23, 20));
+
+    dword = INREG(AUD_OUT_DIG_CNVT_C);
+    printf("AUD_OUT_DIG_CNVT_C  V\t\t\t\t\t%lu\n",		BIT(dword, 1));
+    printf("AUD_OUT_DIG_CNVT_C  VCFG\t\t\t\t%lu\n",		BIT(dword, 2));
+    printf("AUD_OUT_DIG_CNVT_C  PRE\t\t\t\t\t%lu\n",		BIT(dword, 3));
+    printf("AUD_OUT_DIG_CNVT_C  Copy\t\t\t\t%lu\n",		BIT(dword, 4));
+    printf("AUD_OUT_DIG_CNVT_C  NonAudio\t\t\t\t%lu\n",		BIT(dword, 5));
+    printf("AUD_OUT_DIG_CNVT_C  PRO\t\t\t\t\t%lu\n",		BIT(dword, 6));
+    printf("AUD_OUT_DIG_CNVT_C  Level\t\t\t\t%lu\n",		BIT(dword, 7));
+    printf("AUD_OUT_DIG_CNVT_C  Category_Code\t\t\t%lu\n",	BITS(dword, 14, 8));
+    printf("AUD_OUT_DIG_CNVT_C  Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
+    printf("AUD_OUT_DIG_CNVT_C  Stream_ID\t\t\t\t%lu\n",	BITS(dword, 23, 20));
+
+    printf("AUD_OUT_CHAN_MAP  Converter_Channel_MAP	PORTB	PORTC	PORTD\n");
+    for (i = 0; i < 8; i++) {
+	    OUTREG(AUD_OUT_CHAN_MAP, i | (i << 8) | (i << 16));
+	    dword = INREG(AUD_OUT_CHAN_MAP);
+	    printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
+		   1 + BITS(dword,  3,  0),
+		   1 + BITS(dword,  7,  4),
+		   1 + BITS(dword, 15, 12),
+		   1 + BITS(dword, 23, 20));
+    }
+
+    dword = INREG(AUD_OUT_STR_DESC_A);
+    printf("AUD_OUT_STR_DESC_A  Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
+    printf("AUD_OUT_STR_DESC_A  Bits_per_Sample\t\t\t[%#lx] %s\n",
+				BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
+    printf("AUD_OUT_STR_DESC_A  Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
+
+    dword = INREG(AUD_OUT_STR_DESC_B);
+    printf("AUD_OUT_STR_DESC_B  Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
+    printf("AUD_OUT_STR_DESC_B  Bits_per_Sample\t\t\t[%#lx] %s\n",
+				BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
+    printf("AUD_OUT_STR_DESC_B  Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
+
+    dword = INREG(AUD_OUT_STR_DESC_C);
+    printf("AUD_OUT_STR_DESC_C  Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
+    printf("AUD_OUT_STR_DESC_C  Bits_per_Sample\t\t\t[%#lx] %s\n",
+				BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
+    printf("AUD_OUT_STR_DESC_C  Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
+
+    dword = INREG(AUD_PINW_CONNLNG_SEL);
+    printf("AUD_PINW_CONNLNG_SEL  Connection_select_Control_B\t%#lx\n", BITS(dword,  7,  0));
+    printf("AUD_PINW_CONNLNG_SEL  Connection_select_Control_C\t%#lx\n", BITS(dword, 15,  8));
+    printf("AUD_PINW_CONNLNG_SEL  Connection_select_Control_D\t%#lx\n", BITS(dword, 23, 16));
+
+    dword = INREG(AUD_PIN_ELD_CP_VLD);
+    printf("AUD_CNTRL_ST2  CP_ReadyB\t\t\t\t%lu\n",	BIT(dword, 1));
+    printf("AUD_CNTRL_ST2  ELD_validB\t\t\t\t%lu\n",	BIT(dword, 0));
+    printf("AUD_CNTRL_ST2  OUT_enableB\t\t\t\t%lu\n",	BIT(dword, 2));
+    printf("AUD_CNTRL_ST2  CP_ReadyC\t\t\t\t%lu\n",	BIT(dword, 5));
+    printf("AUD_CNTRL_ST2  ELD_validC\t\t\t\t%lu\n",	BIT(dword, 4));
+    printf("AUD_CNTRL_ST2  OUT_enableC\t\t\t\t%lu\n",	BIT(dword, 6));
+    printf("AUD_CNTRL_ST2  CP_ReadyD\t\t\t\t%lu\n",	BIT(dword, 9));
+    printf("AUD_CNTRL_ST2  ELD_validD\t\t\t\t%lu\n",	BIT(dword, 8));
+    printf("AUD_CNTRL_ST2  OUT_enableD\t\t\t\t%lu\n",	BIT(dword, 10));
+
+    dword = INREG(AUD_HDMIW_STATUS);
+    printf("AUD_HDMIW_STATUS  Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 27));
+    printf("AUD_HDMIW_STATUS  Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n",  BIT(dword, 26));
+    printf("AUD_HDMIW_STATUS  Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
+    printf("AUD_HDMIW_STATUS  Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n",  BIT(dword, 28));
+    printf("AUD_HDMIW_STATUS  Conv_C_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
+    printf("AUD_HDMIW_STATUS  Conv_C_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n",  BIT(dword, 30));
+    printf("AUD_HDMIW_STATUS  BCLK/CDCLK_FIFO_Overrun\t\t%lu\n",	 BIT(dword, 25));
+    printf("AUD_HDMIW_STATUS  Function_Reset\t\t\t%lu\n",		 BIT(dword, 24));
+
+    printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
+    dword = INREG(AUD_DIP_ELD_CTRL_ST_A);
+    dword &= ~BITMASK(9, 5);
+    OUTREG(AUD_DIP_ELD_CTRL_ST_A, dword);
+    for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
+	    printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
+    printf("\n");
+
+    printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
+    dword = INREG(AUD_DIP_ELD_CTRL_ST_B);
+    dword &= ~BITMASK(9, 5);
+    OUTREG(AUD_DIP_ELD_CTRL_ST_B, dword);
+    for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
+	    printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
+    printf("\n");
+
+    printf("AUD_HDMIW_HDMIEDID_C HDMI ELD:\n\t");
+    dword = INREG(AUD_DIP_ELD_CTRL_ST_C);
+    dword &= ~BITMASK(9, 5);
+    OUTREG(AUD_DIP_ELD_CTRL_ST_C, dword);
+    for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
+	    printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_C)));
+    printf("\n");
+
+    printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
+    dword = INREG(AUD_DIP_ELD_CTRL_ST_A);
+    dword &= ~BITMASK(20, 18);
+    dword &= ~BITMASK(3, 0);
+    OUTREG(AUD_DIP_ELD_CTRL_ST_A, dword);
+    for (i = 0; i < 8; i++)
+	    printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
+    printf("\n");
+
+    printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
+    dword = INREG(AUD_DIP_ELD_CTRL_ST_B);
+    dword &= ~BITMASK(20, 18);
+    dword &= ~BITMASK(3, 0);
+    OUTREG(AUD_DIP_ELD_CTRL_ST_B, dword);
+    for (i = 0; i < 8; i++)
+	    printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
+    printf("\n");
+
+    printf("AUD_HDMIW_INFOFR_C HDMI audio Infoframe:\n\t");
+    dword = INREG(AUD_DIP_ELD_CTRL_ST_C);
+    dword &= ~BITMASK(20, 18);
+    dword &= ~BITMASK(3, 0);
+    OUTREG(AUD_DIP_ELD_CTRL_ST_C, dword);
+    for (i = 0; i < 8; i++)
+	    printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_C)));
+    printf("\n");
+}
+
 int main(int argc, char **argv)
 {
 	struct pci_device *pci_dev;
@@ -1369,6 +1946,11 @@  int main(int argc, char **argv)
 		intel_get_mmio(pci_dev);
 
 	if (IS_GEN6(devid) || IS_GEN7(devid) || getenv("HAS_PCH_SPLIT")) {
+		if (IS_HASWELL(devid)) {
+			printf("Haswell audio registers:\n\n");
+			dump_hsw();
+			return 0;
+		}
 		printf("%s audio registers:\n\n",
 		       IS_GEN6(devid) ? "SandyBridge" : "IvyBridge");
 		intel_check_pch();