From patchwork Wed Aug 8 15:42:52 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1296581 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id C04413FC23 for ; Wed, 8 Aug 2012 15:43:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9C1F8A09EA for ; Wed, 8 Aug 2012 08:43:00 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f177.google.com (mail-wi0-f177.google.com [209.85.212.177]) by gabe.freedesktop.org (Postfix) with ESMTP id EF17B9EB14 for ; Wed, 8 Aug 2012 08:42:35 -0700 (PDT) Received: by wibhm11 with SMTP id hm11so607783wib.12 for ; Wed, 08 Aug 2012 08:42:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer; bh=6+OYrRlAbRjIergBwLERytZd1zeSn/sqalMlQAWoT/c=; b=fVTYbEdmXHG01HsByCyMGHMzWLRCcXJmjuIX7nuPyslpFmhlHe7E7D/8D9t8U6kCLd QJprZF74ZA8fAS5Nh2ctaDG2PVsMYssKHrbTpJBveZY49hyyBGKHYx6wUJUDuZ6N1JIp bINXHMMKgwFG92uxj0kV41WHPpvasI5s19UK8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=6+OYrRlAbRjIergBwLERytZd1zeSn/sqalMlQAWoT/c=; b=TOcNlj5B5E8TmvCIIZ1cM01/gaZ3AcnpmsmdnpZZCMx7O1E6sjoj9ymQV1mjJMiUTl cLoQYI+2GsKTZmhXAOFpw2/NxdgymQYx5+RjD7y5glxDcYXNbJWdC/Sd3mqqxRFgsqRr YLPi1xEckTC9nmdgZ88Wy19QCZOYnO9Ivc7MQaa+AEufIQzNhcM3DrguOg44IPjDg1QT WIVEBJo0TkX6354e8S01Zu8OmwprNF+wI0MMRUH6lOeUXP09osRZ8zZX4qwmq1Z9cA24 o+SW49CUXF35/VwXK8EkDwcDvV8FtsZEjg+jkhnzS/FLE192jiEo6cmhJMrfQ4ueQyWg 2glQ== Received: by 10.180.84.169 with SMTP id a9mr3733999wiz.8.1344440555029; Wed, 08 Aug 2012 08:42:35 -0700 (PDT) Received: from phenom.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id el6sm5685496wib.8.2012.08.08.08.42.33 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 08 Aug 2012 08:42:34 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 8 Aug 2012 17:42:52 +0200 Message-Id: <1344440572-12411-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 X-Gm-Message-State: ALoCoQnyCeaWDoiVZ74lmZ2R3LljumuDnO+nASdn1RdeohZtlN80wEsSKNocP29URd3rYNrC7Xok Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: fixup desired rps frequency computation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org In commit commit 20b46e59dd102665ce7168baa215e5b1ee66b69b Author: Daniel Vetter Date: Thu Jul 26 11:16:14 2012 +0200 drm/i915: Only set the down rps limit when at the loweset frequency The computation for the new desired frequency was extracted, but since the desired frequency was passed-by value, the adjustments didn't propgate back. Fix this. Signed-off-by: Daniel Vetter Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d0ce894..5050bb8 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2272,13 +2272,13 @@ static void ironlake_disable_drps(struct drm_device *dev) * ourselves, instead of doing a rmw cycle (which might result in us clearing * all limits and the gpu stuck at whatever frequency it is at atm). */ -static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val) +static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val) { u32 limits; limits = 0; - if (val >= dev_priv->max_delay) - val = dev_priv->max_delay; + if (*val >= dev_priv->max_delay) + *val = dev_priv->max_delay; limits |= dev_priv->max_delay << 24; /* Only set the down limit when we've reached the lowest level to avoid @@ -2287,8 +2287,8 @@ static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val) * the hw runs at the minimal clock before selecting the desired * frequency, if the down threshold expires in that window we will not * receive a down interrupt. */ - if (val <= dev_priv->min_delay) { - val = dev_priv->min_delay; + if (*val <= dev_priv->min_delay) { + *val = dev_priv->min_delay; limits |= dev_priv->min_delay << 16; } @@ -2298,7 +2298,7 @@ static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val) void gen6_set_rps(struct drm_device *dev, u8 val) { struct drm_i915_private *dev_priv = dev->dev_private; - u32 limits = gen6_rps_limits(dev_priv, val); + u32 limits = gen6_rps_limits(dev_priv, &val); if (val == dev_priv->cur_delay) return;