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[2/8] drm/i915: set the DDI sync polarity bits

Message ID 1344446134-3704-3-git-send-email-przanoni@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Paulo Zanoni Aug. 8, 2012, 5:15 p.m. UTC 
From: Paulo Zanoni <paulo.r.zanoni@intel.com>

During my tests, everything worked even if the wrong polarity was set.
Still, we should try to set the correct values.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 2 ++
 drivers/gpu/drm/i915/intel_ddi.c | 6 ++++++
 2 files changed, 8 insertions(+)
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Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 97f00fb..896b279 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4312,6 +4312,8 @@ 
 #define  PIPE_DDI_BPC_10				(1<<20)
 #define  PIPE_DDI_BPC_6					(2<<20)
 #define  PIPE_DDI_BPC_12				(3<<20)
+#define  PIPE_DDI_PVSYNC			(1<<17)
+#define  PIPE_DDI_PHSYNC			(1<<16)
 #define  PIPE_DDI_BFI_ENABLE			(1<<4)
 #define  PIPE_DDI_PORT_WIDTH_X1			(0<<1)
 #define  PIPE_DDI_PORT_WIDTH_X2			(1<<1)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0d7acd7..1fbd67c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -727,6 +727,7 @@  void intel_ddi_mode_set(struct drm_encoder *encoder,
 	temp &= ~PIPE_DDI_PORT_MASK;
 	temp &= ~PIPE_DDI_BPC_12;
 	temp &= ~PIPE_DDI_MODE_SELECT_MASK;
+	temp &= ~(PIPE_DDI_PVSYNC | PIPE_DDI_PHSYNC);
 	temp |= PIPE_DDI_SELECT_PORT(port) |
 			((intel_crtc->bpp > 24) ?
 				PIPE_DDI_BPC_12 :
@@ -738,6 +739,11 @@  void intel_ddi_mode_set(struct drm_encoder *encoder,
 	else
 		temp |= PIPE_DDI_MODE_SELECT_DVI;
 
+	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+		temp |= PIPE_DDI_PVSYNC;
+	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+		temp |= PIPE_DDI_PHSYNC;
+
 	I915_WRITE(DDI_FUNC_CTL(pipe), temp);
 
 	intel_hdmi->set_infoframes(encoder, adjusted_mode);