From patchwork Wed Aug 8 21:35:34 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1297661 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 24CAA3FCFC for ; Wed, 8 Aug 2012 21:21:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 05AB6A0B29 for ; Wed, 8 Aug 2012 14:21:00 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f177.google.com (mail-wi0-f177.google.com [209.85.212.177]) by gabe.freedesktop.org (Postfix) with ESMTP id D66F5A0ABA for ; Wed, 8 Aug 2012 14:19:09 -0700 (PDT) Received: by wibhm11 with SMTP id hm11so832301wib.12 for ; Wed, 08 Aug 2012 14:19:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=1eeC643xsnEVwj9aXvYsajJIKYtfuHuV9F9NGjOiH+s=; b=YuykgapMoWtlwT6/noSiWhd2Lngbbl5Y8gb5TOEkUuyQelYRiOXU0h9WVDRsOAKnrj sDKpK7o7jo4aRXcIYvPiD+sS/96pnD/XKCMFYXPPRaY5ni6EqS3PdoVd6+w0sX0vNdUy Ws+LhH5SpyRO6kBx8RCQoqIzZFtSb1N8YClx8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=1eeC643xsnEVwj9aXvYsajJIKYtfuHuV9F9NGjOiH+s=; b=L3J41GfmsoIhtT4TMIbe5aygq4p/osGdnGBOeghwCGeCyWDU4iQVRYUbA1LSpKY+oy 6gLOnPmYwMkB1XViDD3M9YgPzmdvvqcsdiGk+1b4LuZIhBKK+4EXD5tb+jSKT+qJWe4P HZ8Xnndp5HiTDfOLOWSbGMalZ29/pbm4RZgjFTKt0uT3WuGl1U9xuoVb2I0eIcGEhScJ /sDvtr7PiSd/lywAuAkEbPC8Jfv6Q3TWW9j4XT077ApPKkWFs4ytKiJTuOz5+hwOCeRD JCV6/o6QoLzjxovxImz+NaudXR0Nv/1Ot9oMYKiXNhrqPpvQzC1j2heAE+nIjL4pzxnK W0rA== Received: by 10.180.83.66 with SMTP id o2mr869983wiy.14.1344460748993; Wed, 08 Aug 2012 14:19:08 -0700 (PDT) Received: from hummel.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id o2sm10646321wiz.11.2012.08.08.14.19.07 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 08 Aug 2012 14:19:08 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 8 Aug 2012 23:35:34 +0200 Message-Id: <1344461740-1231-3-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1344461740-1231-1-git-send-email-daniel.vetter@ffwll.ch> References: <1344461740-1231-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQkPIx4t3kOUedb5N58jojeiB1SFEEunRmh+yHX8/Cpq7GeEmIgmnPdeCjbf9MBkUd7o1VF/ Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 2/8] drm/i915: fixup up debugfs rps state handling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org - Take the dev->struct_mutex around access the corresponding state (and adjusting the rps hw state). - Add an assert to gen6_set_rps to ensure we don't forget about this in the future. - Don't set up the min/max_freq files if it doesn't apply to the hw. And do the same for the gen6+ cache sharing file while at it. v2: Move the gen6+ checks into the read/write callbacks. Thanks to the awesome drm midlayer we can't check that when registering the debugfs files, because the driver is not yet fully set up, specifically the ->load callback hasn't run yet. Oh how I despise this disaster ... v3: Also add a WARN_ON(mutex_is_locked) in set_rps to check the locking. Reviewed-by: Ben Widawsky (for v2) Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 27 +++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_pm.c | 2 ++ 2 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 1312b79..2499610 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1710,8 +1710,13 @@ i915_max_freq_read(struct file *filp, char buf[80]; int len; + if (!(IS_GEN6(dev) || IS_GEN7(dev))) + return -ENODEV; + + mutex_lock(&dev->struct_mutex); len = snprintf(buf, sizeof(buf), "max freq: %d\n", dev_priv->max_delay * 50); + mutex_unlock(&dev->struct_mutex); if (len > sizeof(buf)) len = sizeof(buf); @@ -1730,6 +1735,9 @@ i915_max_freq_write(struct file *filp, char buf[20]; int val = 1; + if (!(IS_GEN6(dev) || IS_GEN7(dev))) + return -ENODEV; + if (cnt > 0) { if (cnt > sizeof(buf) - 1) return -EINVAL; @@ -1743,12 +1751,14 @@ i915_max_freq_write(struct file *filp, DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val); + mutex_lock(&dev->struct_mutex); /* * Turbo will still be enabled, but won't go above the set value. */ dev_priv->max_delay = val / 50; gen6_set_rps(dev, val / 50); + mutex_unlock(&dev->struct_mutex); return cnt; } @@ -1770,8 +1780,13 @@ i915_min_freq_read(struct file *filp, char __user *ubuf, size_t max, char buf[80]; int len; + if (!(IS_GEN6(dev) || IS_GEN7(dev))) + return -ENODEV; + + mutex_lock(&dev->struct_mutex); len = snprintf(buf, sizeof(buf), "min freq: %d\n", dev_priv->min_delay * 50); + mutex_unlock(&dev->struct_mutex); if (len > sizeof(buf)) len = sizeof(buf); @@ -1788,6 +1803,9 @@ i915_min_freq_write(struct file *filp, const char __user *ubuf, size_t cnt, char buf[20]; int val = 1; + if (!(IS_GEN6(dev) || IS_GEN7(dev))) + return -ENODEV; + if (cnt > 0) { if (cnt > sizeof(buf) - 1) return -EINVAL; @@ -1801,12 +1819,14 @@ i915_min_freq_write(struct file *filp, const char __user *ubuf, size_t cnt, DRM_DEBUG_DRIVER("Manually setting min freq to %d\n", val); + mutex_lock(&dev->struct_mutex); /* * Turbo will still be enabled, but won't go below the set value. */ dev_priv->min_delay = val / 50; gen6_set_rps(dev, val / 50); + mutex_unlock(&dev->struct_mutex); return cnt; } @@ -1831,6 +1851,9 @@ i915_cache_sharing_read(struct file *filp, u32 snpcr; int len; + if (!(IS_GEN6(dev) || IS_GEN7(dev))) + return -ENODEV; + mutex_lock(&dev_priv->dev->struct_mutex); snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); mutex_unlock(&dev_priv->dev->struct_mutex); @@ -1857,6 +1880,9 @@ i915_cache_sharing_write(struct file *filp, u32 snpcr; int val = 1; + if (!(IS_GEN6(dev) || IS_GEN7(dev))) + return -ENODEV; + if (cnt > 0) { if (cnt > sizeof(buf) - 1) return -EINVAL; @@ -2061,6 +2087,7 @@ int i915_debugfs_init(struct drm_minor *minor) &i915_cache_sharing_fops); if (ret) return ret; + ret = i915_debugfs_create(minor->debugfs_root, minor, "i915_ring_stop", &i915_ring_stop_fops); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ad90579..dece479 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2300,6 +2300,8 @@ void gen6_set_rps(struct drm_device *dev, u8 val) struct drm_i915_private *dev_priv = dev->dev_private; u32 limits = gen6_rps_limits(dev_priv, &val); + WARN_ON(!mutex_is_locked(&dev->struct_mutex)); + if (val == dev_priv->cur_delay) return;