From patchwork Wed Aug 8 21:35:40 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1297721 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 4B5613FCFC for ; Wed, 8 Aug 2012 21:24:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 28F23A0B00 for ; Wed, 8 Aug 2012 14:24:53 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 089ECA0AE2 for ; Wed, 8 Aug 2012 14:19:17 -0700 (PDT) Received: by mail-we0-f177.google.com with SMTP id r3so863605wey.36 for ; Wed, 08 Aug 2012 14:19:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=2jQnigIB4X7jdt0rmxBizoWteLC6c4orWdKTD5KQ/O8=; b=Q5oOzcEF9j9C1Jfqkp129zd2igNOzMRsHL47zlwmyFpmjSbQI1ofGcRKQy6UbnefSP Fz2ULcu9F7ehiwSQ1onTFPTf5Nlk7L+gHHczq0dqAcFI2mfLSoXEkaGkILIEiCx1fIrl RLCXXOcAApXKLRfFglbvhPXev+Gq6woUgsjUQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=2jQnigIB4X7jdt0rmxBizoWteLC6c4orWdKTD5KQ/O8=; b=OX5ck7AtdkU3Nj9qp2c4qim8GhVubVLguHvjMZNVvnYxNx4FqlBnp68IbOFgan04ND apLXC0qJFyMfEzV41lfKoEQB8q6/bBge1a8Qb0pzz7snCvYmW6I5hVl29NhodKRcBCNp VL8nYFxEROlLci2TSYemidcHTfdjHZrVQOp2T/jYrKyVyBPnVZJQVpSYVAPE5BYA61SI CxtpRkm44sb/T5qPZ1RRgA3CeP4h2iLy++c8RI4TeS2RigqFFIThknCbIsaLMFvEJX0U 3y1Jzc5FdS1fZCUzlBdcEjqcCGwt4yOv9dBCeZntcH6LrnJQZ04z68xKfBqwgr+ty+BM Z5+w== Received: by 10.180.98.200 with SMTP id ek8mr958481wib.0.1344460757727; Wed, 08 Aug 2012 14:19:17 -0700 (PDT) Received: from hummel.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id o2sm10646321wiz.11.2012.08.08.14.19.16 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 08 Aug 2012 14:19:17 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 8 Aug 2012 23:35:40 +0200 Message-Id: <1344461740-1231-9-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1344461740-1231-1-git-send-email-daniel.vetter@ffwll.ch> References: <1344461740-1231-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQlwJpavZbzuo2+jCtcKsAUoSqIv0VY8JoK00+1bZEt74NwP/DueWy6KLLfKvC/2PES0SrEQ Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 8/8] drm/i915: enable rc6 on ilk again X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org I have the faint hope that the total absence of any locking for the rps code wasn't too good an idea and could very well have caused some rc6 related regressions. Unfortunately we've never managed to reproduce these issues on any of our own machines, so the only way to go about this is to enable it and see what happens. While at it, kill some stale comments and improve the logging. Signed-Off-by: Daniel Vetter Acked-by: Ben Widawsky --- drivers/gpu/drm/i915/intel_pm.c | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index eff0753..a87c625 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2361,31 +2361,26 @@ static void gen6_disable_rps(struct drm_device *dev) int intel_enable_rc6(const struct drm_device *dev) { - /* - * Respect the kernel parameter if it is set - */ + /* Respect the kernel parameter if it is set */ if (i915_enable_rc6 >= 0) return i915_enable_rc6; - /* - * Disable RC6 on Ironlake - */ - if (INTEL_INFO(dev)->gen == 5) - return 0; + if (INTEL_INFO(dev)->gen == 5) { + DRM_DEBUG_DRIVER("Ironlake: only RC6 available\n"); + return INTEL_RC6_ENABLE; + } - /* On Haswell, only RC6 is available. So let's enable it by default to - * provide better testing and coverage since the beginning. - */ - if (IS_HASWELL(dev)) + if (IS_HASWELL(dev)) { + DRM_DEBUG_DRIVER("Haswell: only RC6 available\n"); return INTEL_RC6_ENABLE; + } - /* - * Disable rc6 on Sandybridge - */ + /* snb/ivb have more than one rc6 state. */ if (INTEL_INFO(dev)->gen == 6) { DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n"); return INTEL_RC6_ENABLE; } + DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n"); return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); }