From patchwork Wed Aug 15 08:41:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1324781 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 07AEEDFFED for ; Wed, 15 Aug 2012 08:42:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1A205A0CA4 for ; Wed, 15 Aug 2012 01:42:15 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 70B04A0DCA for ; Wed, 15 Aug 2012 01:41:34 -0700 (PDT) Received: by weyr3 with SMTP id r3so922276wey.36 for ; Wed, 15 Aug 2012 01:41:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer; bh=6MFDacrpaQ2q1DU6/tVMEgvYRKfMfQqv2OhwZGmGf7E=; b=QEf6LM5l9Qjh5CJJ8hNROBdPbBNIR2cW2eEEGpmF6U/+HFa38fr/JPgPcsPtvE4u7i 8RoOgPTA0RuxuxPL9+QlUiNV4834eX+qKEiYIGQRffWQANHh+uNZ1FTPKfcIItfbW9+S VPqEQR1MDBcKYU+xUjgRwY9B5TWNM7hXnSejI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=6MFDacrpaQ2q1DU6/tVMEgvYRKfMfQqv2OhwZGmGf7E=; b=m19RkjDAjhCCRAYg8dhDaOo6Js6r/sX1pPBSKyBKoPa1NWnAOfpz5JtQn/Pz6p2DwW lssHiWUYnOv+Ewvce1fLTdgZV/tYFMUIvhluqKK+y8KqafsFq2G0yg73APgvKKf9BlI/ lu4+UYZ8RANFr/4PjTpYfE5j/uIOI7+qL6mrT1CKXbU7Hs7ms7WIlexcIZNHafISMPbQ c/9mgkjVskFzg+j7xbbgAnxLNMylFx6tiwpTXB5b9NPeSyWcY7atBH/DCOLaV9nw2fqv lG2ftyUpN9pCadlhKZtxfsp1lo7eDl9QdCbIwqmT+0DLkaRdgcS4NzjEC4VLjrTfsxeq SvAg== Received: by 10.180.97.33 with SMTP id dx1mr35254951wib.18.1345020093263; Wed, 15 Aug 2012 01:41:33 -0700 (PDT) Received: from phenom.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id q4sm27317230wix.9.2012.08.15.01.41.31 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 15 Aug 2012 01:41:32 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 15 Aug 2012 10:41:45 +0200 Message-Id: <1345020105-5933-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 X-Gm-Message-State: ALoCoQnfn7H6qjnHf5KY/SLAnyg1YpxEOVLg99OukcADgWqEP/CHTm2svTcq4ok43G5UMNizlweM Cc: Daniel Vetter , stable@vger.kernel.org Subject: [Intel-gfx] [PATCH] drm/i915: use hsw rps tuning values everywhere on gen6+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org James Bottomley reported [1] a massive power regression, due to the enabling of semaphores by default in 3.5. A workaround for him is to again disable semaphores. And indeed, his system has a very hard time to entre rc6 with semaphores enabled. Ben Widawsky run around with a kill-a-watt a lot and noticed: - There are indeed a few rare systems that seem to have a hard time entering rc6 when desktop-idle. - One machine, The Indestructible Toshiba regressed in this behaviour between 3.5 and 3.6 in a merge commit! So rc6 behaviour with the current setting seems to be highly timing dependent and not robust at all. - The behaviour James reported wrt semaphores seems to be a freak timing thing that only happens on his specific machine, confirming that enabling semaphores shouldn't reduce rc6 residency. Now furthermore the Google ChromeOS guys reported [2] a while ago that at least on some machines a simply a blinking cursor can keep the gpu turbo at the highest frequency. This is because the current rps limits used on snb/ivb are highly asymmetric. On the theory that gpu turbo and rc6 tuning values are related, we've tried whether the much saner looking (since much less asymmetric) rps tuning values used for hsw would also help entering rc6 more robustly. And it seems to work. Reference[1]: http://lists.freedesktop.org/archives/dri-devel/2012-July/025675.html Reference[2]: http://lists.freedesktop.org/archives/intel-gfx/2012-July/018692.html Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53393 Tested-by: Ben Widawsky Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter Acked-by: Paul Menzel --- drivers/gpu/drm/i915/intel_pm.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d64dffb..cf10a1d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2482,17 +2482,10 @@ static void gen6_enable_rps(struct drm_device *dev) dev_priv->rps.max_delay << 24 | dev_priv->rps.min_delay << 16); - if (IS_HASWELL(dev)) { - I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); - I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); - I915_WRITE(GEN6_RP_UP_EI, 66000); - I915_WRITE(GEN6_RP_DOWN_EI, 350000); - } else { - I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000); - I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000); - I915_WRITE(GEN6_RP_UP_EI, 100000); - I915_WRITE(GEN6_RP_DOWN_EI, 5000000); - } + I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); + I915_WRITE(GEN6_RP_UP_EI, 66000); + I915_WRITE(GEN6_RP_DOWN_EI, 350000); I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); I915_WRITE(GEN6_RP_CONTROL,