From patchwork Tue Aug 28 22:06:52 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1382901 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 321153FDF5 for ; Tue, 28 Aug 2012 22:23:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 075129E95A for ; Tue, 28 Aug 2012 15:23:01 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yx0-f177.google.com (mail-yx0-f177.google.com [209.85.213.177]) by gabe.freedesktop.org (Postfix) with ESMTP id AEFE19EB1F for ; Tue, 28 Aug 2012 15:08:02 -0700 (PDT) Received: by mail-yx0-f177.google.com with SMTP id q9so1203648yen.36 for ; Tue, 28 Aug 2012 15:08:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=z0wyvrvLUfPm62WAJaCvLdaJItaclwogIMZThlc4s4E=; b=mlQuuLb/ZadKiPb/UpoeGN74DuTqV8FTt7uMqSd8vxl7t90daJdqIswLEhSTsB+t/x e/31HA9UZUTUAqjmXDpUe53H8azrAZP0b+rW+pQNCC+xyDMAvOmnN6X/IR7LmET1o5rg bkAIei4egwsL8TtnfFXGaJdtmTzgNolLd9BG6UhC8ycDKK/0ylbU10rVImObFKI8YuUi wMY/KHRdOVIdKeSTipa2g//erNOiLhWC0c0cTTImDaBvEcdu7uX9SfIglxI737boosL0 WUcCyiHBBWMr2CX4mhXc9rPPHWu2c0+JmyhULd7IAdLw2zsWc8UgfvlqkEJpM4/rbhDR qDoA== Received: by 10.236.77.229 with SMTP id d65mr15272092yhe.124.1346191682644; Tue, 28 Aug 2012 15:08:02 -0700 (PDT) Received: from vicky.domain.invalid (189.114.178.236.dynamic.adsl.gvt.net.br. [189.114.178.236]) by mx.google.com with ESMTPS id z3sm4434172anj.20.2012.08.28.15.08.00 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 28 Aug 2012 15:08:02 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 28 Aug 2012 19:06:52 -0300 Message-Id: <1346191621-12996-22-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1346191621-12996-1-git-send-email-przanoni@gmail.com> References: <1346191621-12996-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [RFC 21/30] drm/i915: enable eDP on Haswell X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++++++++++-- drivers/gpu/drm/i915/intel_dp.c | 2 +- 3 files changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4bf4cc9..56f8617 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4399,6 +4399,9 @@ #define PIPE_DDI_BPC_12 (3<<20) #define PIPE_DDI_PVSYNC (1<<17) #define PIPE_DDI_PHSYNC (1<<16) +#define PIPE_DDI_INPUT_A_ONOFF (4<<12) +#define PIPE_DDI_INPUT_B_ONOFF (5<<12) +#define PIPE_DDI_INPUT_C_ONOFF (6<<12) #define PIPE_DDI_BFI_ENABLE (1<<4) #define PIPE_DDI_PORT_WIDTH_X1 (0<<1) #define PIPE_DDI_PORT_WIDTH_X2 (1<<1) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index ad1fb5f..44bf9e6 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -236,6 +236,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port) case PORT_A: /* We don't handle eDP and DP yet */ DRM_DEBUG_DRIVER("Found digital output on DDI port A\n"); + intel_dp_init(dev, DDI_BUF_CTL_A, PORT_A); break; /* Assume that the ports B, C and D are working in HDMI mode for now */ case PORT_B: @@ -655,6 +656,7 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc) for_each_encoder_on_crtc(dev, crtc, intel_encoder) { switch (intel_encoder->type) { case INTEL_OUTPUT_DISPLAYPORT: + case INTEL_OUTPUT_EDP: is_dp = true; intel_dp = enc_to_intel_dp(&intel_encoder->base); port = intel_dp->port; @@ -810,7 +812,8 @@ static void intel_ddi_enable_pipe(struct intel_encoder *intel_encoder) port = intel_dp->port; } - I915_WRITE(PIPE_CLK_SEL(pipe), PIPE_CLK_SEL_PORT(port)); + if (transcoder != TRANSCODER_EDP) + I915_WRITE(PIPE_CLK_SEL(pipe), PIPE_CLK_SEL_PORT(port)); func_val = PIPE_DDI_FUNC_ENABLE | PIPE_DDI_SELECT_PORT(port); msa_val = PIPE_MSA_SYNC_CLK; @@ -842,6 +845,18 @@ static void intel_ddi_enable_pipe(struct intel_encoder *intel_encoder) if (mode->flags & DRM_MODE_FLAG_PHSYNC) func_val |= PIPE_DDI_PHSYNC; + switch (pipe) { + case PIPE_A: + func_val |= PIPE_DDI_INPUT_A_ONOFF; + break; + case PIPE_B: + func_val |= PIPE_DDI_INPUT_B_ONOFF; + break; + case PIPE_C: + func_val |= PIPE_DDI_INPUT_C_ONOFF; + break; + } + if (intel_encoder->type == INTEL_OUTPUT_HDMI) { if (intel_hdmi->has_hdmi_sink) func_val |= PIPE_DDI_MODE_SELECT_HDMI; @@ -997,7 +1012,8 @@ static void intel_ddi_disable_pipe(struct drm_i915_private *dev_priv, temp |= PIPE_DDI_PORT_NONE; I915_WRITE(DDI_FUNC_CTL(transcoder), temp); - I915_WRITE(PIPE_CLK_SEL(pipe), PIPE_CLK_SEL_DISABLED); + if (transcoder != TRANSCODER_EDP) + I915_WRITE(PIPE_CLK_SEL(pipe), PIPE_CLK_SEL_DISABLED); } static void intel_ddi_disable_port(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 11c7d08..afee975 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -384,7 +384,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, * clock divider. */ if (is_cpu_edp(intel_dp)) { - if (IS_GEN6(dev) || IS_GEN7(dev)) + if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_HASWELL(dev)) aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ else aux_clock_divider = 225; /* eDP input clock at 450Mhz */