From patchwork Wed Sep 5 19:24:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1410771 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 3F5F8DF28C for ; Wed, 5 Sep 2012 20:32:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 337299E9FF for ; Wed, 5 Sep 2012 13:32:32 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id BA1569E769 for ; Wed, 5 Sep 2012 13:32:02 -0700 (PDT) Received: by weyr3 with SMTP id r3so688524wey.36 for ; Wed, 05 Sep 2012 13:32:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer; bh=XjNPtV5YwgW7p+nB+lrMaPkEJ4vmHTHJueLWApWPUI8=; b=hO5p04Rg1lQv3QkliZTAaN/Tf21c93igHmybWkd+wjPjwwj1wSCiIYSSteeiUYRcX7 zkDqp3mSPwbnxyjXPcwfv5PP7+3yib9ZJVkvs1pR76rX+qIENA9fJEDun64CH12BjgqV PLO3X1rINqx1vtlPh2JeJ27zUgGkYu1VGy2Qg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=XjNPtV5YwgW7p+nB+lrMaPkEJ4vmHTHJueLWApWPUI8=; b=YlZOZ2z5iVjxd28rcy64BwKS/ziHun1xyIquWvWLOtLSaejlflxNN7hG6RVKedOiPi fWdoZZKY7NZPrzqMNL/j1+mrJmcOS9bfEShRsngQavRWmNqFE53mwrXFFfnReg0so67Z xuiS9ZF1XF27CzrOVk30kqUYhgdxvPcZy1c/k2ks8oQp98tZXeq3y5oquGZzGasXY+GA HTPqDsnwZo3mPzvVFz4PAddXLpu7C0sNFzrociSVjeJEjxNMPUCrWArjMBEolliKcE33 sGb8ElFn1hrxKi0cM3aQuU+Gv7kVBhcgqkYURB/C7IHn0m15CMDQgbyz7meOmy5NFYf/ CViw== Received: by 10.180.99.196 with SMTP id es4mr40501617wib.18.1346877121581; Wed, 05 Sep 2012 13:32:01 -0700 (PDT) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id ef5sm80868wib.3.2012.09.05.13.31.59 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 05 Sep 2012 13:32:00 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 5 Sep 2012 21:24:39 +0200 Message-Id: <1346873081-1305-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.2 X-Gm-Message-State: ALoCoQklRMDGzQlkV63I5x5eESsh2RPnQJfjua5HraMCbn/J3qxQ7mzeZAv6o1wgegr+bLyEUItz Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 1/3] drm/i915: extract gmbus_wait_hw_status X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org The gmbus interrupt generation is rather fiddly: We can only ever enable one interrupt source (but we always want to check for NAK in addition to the real bit). And the bits in the gmbus status register don't map at all to the bis in the irq register. To prepare for this mess, start by extracting the hw status wait loop into it's own function, consolidate the NAK error handling a bit. To keep things flexible, pass in the status bit we care about (in addition to any NAK signalling). Signed-off-by: Daniel Vetter Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_i2c.c | 52 +++++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index b9755f6..3a90b87 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -204,6 +204,24 @@ intel_gpio_setup(struct intel_gmbus *bus, u32 pin) } static int +gmbus_wait_hw_status(struct drm_i915_private *dev_priv, + u32 gmbus2_status) +{ + int ret; + int reg_offset = dev_priv->gpio_mmio_base; + u32 gmbus2; + + ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & + (GMBUS_SATOER | gmbus2_status), + 50); + + if (gmbus2 & GMBUS_SATOER) + return -ENXIO; + + return ret; +} + +static int gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, u32 gmbus1_index) { @@ -220,15 +238,10 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, while (len) { int ret; u32 val, loop = 0; - u32 gmbus2; - ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & - (GMBUS_SATOER | GMBUS_HW_RDY), - 50); + ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY); if (ret) - return -ETIMEDOUT; - if (gmbus2 & GMBUS_SATOER) - return -ENXIO; + return ret; val = I915_READ(GMBUS3 + reg_offset); do { @@ -262,7 +275,6 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); while (len) { int ret; - u32 gmbus2; val = loop = 0; do { @@ -271,13 +283,9 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) I915_WRITE(GMBUS3 + reg_offset, val); - ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & - (GMBUS_SATOER | GMBUS_HW_RDY), - 50); + ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY); if (ret) - return -ETIMEDOUT; - if (gmbus2 & GMBUS_SATOER) - return -ENXIO; + return ret; } return 0; } @@ -346,8 +354,6 @@ gmbus_xfer(struct i2c_adapter *adapter, I915_WRITE(GMBUS0 + reg_offset, bus->reg0); for (i = 0; i < num; i++) { - u32 gmbus2; - if (gmbus_is_index_read(msgs, i, num)) { ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); i += 1; /* set i to the index of the read xfer */ @@ -362,13 +368,11 @@ gmbus_xfer(struct i2c_adapter *adapter, if (ret == -ENXIO) goto clear_err; - ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & - (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), - 50); + ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE); + if (ret == -ENXIO) + goto clear_err; if (ret) goto timeout; - if (gmbus2 & GMBUS_SATOER) - goto clear_err; } /* Generate a STOP condition on the bus. Note that gmbus can't generata @@ -381,8 +385,7 @@ gmbus_xfer(struct i2c_adapter *adapter, * We will re-enable it at the start of the next xfer, * till then let it sleep. */ - if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, - 10)) { + if (gmbus_wait_hw_status(dev_priv, GMBUS_ACTIVE)) { DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", adapter->name); ret = -ETIMEDOUT; @@ -406,8 +409,7 @@ clear_err: * it's slow responding and only answers on the 2nd retry. */ ret = -ENXIO; - if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, - 10)) { + if (gmbus_wait_hw_status(dev_priv, GMBUS_ACTIVE)) { DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", adapter->name); ret = -ETIMEDOUT;