From patchwork Thu Sep 6 07:09:59 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1412471 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id F3F37DFFCF for ; Thu, 6 Sep 2012 08:17:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BBAA39EEF3 for ; Thu, 6 Sep 2012 01:17:40 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-bk0-f49.google.com (mail-bk0-f49.google.com [209.85.214.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 07F519EC00 for ; Thu, 6 Sep 2012 01:17:24 -0700 (PDT) Received: by bkcji2 with SMTP id ji2so643778bkc.36 for ; Thu, 06 Sep 2012 01:17:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer; bh=X7hqJ5l93z5y1AQEmq3bkL88XQI6RnZa3jBE21Pryz8=; b=Geyb9qAAklvdFt5pqsollgKupNPNDOGr2Y/X5EidqRVgu27A+QyVliKZBvQ2fIqlIq MlZ3c4WcAnCDRwGmDcj58ScfZq00TBwHsGu5So1ZgIIyg95/aJuUO39nLnXtWVJFHAkU GxHJnjuDzVoc/FMVJMLsuIApOCPVNe+jHWJFQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=X7hqJ5l93z5y1AQEmq3bkL88XQI6RnZa3jBE21Pryz8=; b=YR6LXRIislJkYXNjEtP7PE8i/Mot2Y010kl1ZLSlaSLgiJdPYVibXT1aJNO/i8AtT3 eWHFrd7VhFkQCE8oUZkAUc3niMPN0zjUqCgNvCaLOm4Y6TxzaGwqktJ9MB9JAAkUllTt +YLszRYvVeM42D/oPLcAWOZCqX9ts7mQie+wg3T5nfcrykrOzH2lWDnt7/z9lSF5h+UL RVaglBZSyefg/D8moUs8oEvEjHaTKw+Tqrke7JwCNRIm6an27t26Qwa2843t/6oHfZqk 7n3C/1GGB0NpUQO9O7rljwoGE9DCLxgFSo0UJqh6OvuvzIEDRxoiiQRsc1K6hSdY/wLG F4Ng== Received: by 10.205.127.77 with SMTP id gz13mr349319bkc.17.1346919443611; Thu, 06 Sep 2012 01:17:23 -0700 (PDT) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id hg13sm485182bkc.7.2012.09.06.01.17.21 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 06 Sep 2012 01:17:22 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 6 Sep 2012 09:09:59 +0200 Message-Id: <1346915402-9399-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.2 X-Gm-Message-State: ALoCoQlav0L7B9Dvbrof1Und3MtofH1ki9s0FPg5gO1lEea/2/PLfoMBwpPiuitoeXmtkgnd7alI Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 1/4] drm/i915: extract gmbus_wait_hw_status X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org The gmbus interrupt generation is rather fiddly: We can only ever enable one interrupt source (but we always want to check for NAK in addition to the real bit). And the bits in the gmbus status register don't map at all to the bis in the irq register. To prepare for this mess, start by extracting the hw status wait loop into it's own function, consolidate the NAK error handling a bit. To keep things flexible, pass in the status bit we care about (in addition to any NAK signalling). v2: I've failed to notice that the sens of GMBUS_ACTIVE is inverted, Chris Wilson gladly pointed that out for me. To keep things simple, ignore that case for now (we only need to idle the gmbus controller at the end of an entire i2c transaction, not after every message). Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_i2c.c | 46 ++++++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index b9755f6..57decac 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -204,6 +204,24 @@ intel_gpio_setup(struct intel_gmbus *bus, u32 pin) } static int +gmbus_wait_hw_status(struct drm_i915_private *dev_priv, + u32 gmbus2_status) +{ + int ret; + int reg_offset = dev_priv->gpio_mmio_base; + u32 gmbus2; + + ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & + (GMBUS_SATOER | gmbus2_status), + 50); + + if (gmbus2 & GMBUS_SATOER) + return -ENXIO; + + return ret; +} + +static int gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, u32 gmbus1_index) { @@ -220,15 +238,10 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, while (len) { int ret; u32 val, loop = 0; - u32 gmbus2; - ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & - (GMBUS_SATOER | GMBUS_HW_RDY), - 50); + ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY); if (ret) - return -ETIMEDOUT; - if (gmbus2 & GMBUS_SATOER) - return -ENXIO; + return ret; val = I915_READ(GMBUS3 + reg_offset); do { @@ -262,7 +275,6 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); while (len) { int ret; - u32 gmbus2; val = loop = 0; do { @@ -271,13 +283,9 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) I915_WRITE(GMBUS3 + reg_offset, val); - ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & - (GMBUS_SATOER | GMBUS_HW_RDY), - 50); + ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY); if (ret) - return -ETIMEDOUT; - if (gmbus2 & GMBUS_SATOER) - return -ENXIO; + return ret; } return 0; } @@ -346,8 +354,6 @@ gmbus_xfer(struct i2c_adapter *adapter, I915_WRITE(GMBUS0 + reg_offset, bus->reg0); for (i = 0; i < num; i++) { - u32 gmbus2; - if (gmbus_is_index_read(msgs, i, num)) { ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); i += 1; /* set i to the index of the read xfer */ @@ -362,13 +368,11 @@ gmbus_xfer(struct i2c_adapter *adapter, if (ret == -ENXIO) goto clear_err; - ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & - (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), - 50); + ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE); + if (ret == -ENXIO) + goto clear_err; if (ret) goto timeout; - if (gmbus2 & GMBUS_SATOER) - goto clear_err; } /* Generate a STOP condition on the bus. Note that gmbus can't generata