diff mbox

[4/7] drm/i915: POSTING_READ the new rps value

Message ID 1347072225-10654-5-git-send-email-ben@bwidawsk.net (mailing list archive)
State Accepted
Headers show

Commit Message

Ben Widawsky Sept. 8, 2012, 2:43 a.m. UTC 
In order to keep our cached values in sync with the hardware, we need a
posting read here.

CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Chris Wilson Sept. 9, 2012, 6:26 p.m. UTC | #1 
On Fri,  7 Sep 2012 19:43:41 -0700, Ben Widawsky <ben@bwidawsk.net> wrote:
> In order to keep our cached values in sync with the hardware, we need a
> posting read here.
> 
> CC: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

Yes, a POSTING_READ does look required here.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 36c6409..4e86037 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2338,6 +2338,8 @@  void gen6_set_rps(struct drm_device *dev, u8 val)
 	 */
 	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
 
+	POSTING_READ(GEN6_RPNSWREQ);
+
 	dev_priv->rps.cur_delay = val;
 
 	trace_intel_gpu_freq_change(val * 50);