From patchwork Sun Sep 9 09:00:41 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1427621 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id A10904025E for ; Sun, 9 Sep 2012 10:09:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8B18A9EC2B for ; Sun, 9 Sep 2012 03:09:29 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wg0-f43.google.com (mail-wg0-f43.google.com [74.125.82.43]) by gabe.freedesktop.org (Postfix) with ESMTP id 692399F368 for ; Sun, 9 Sep 2012 03:08:15 -0700 (PDT) Received: by wgbdr1 with SMTP id dr1so835352wgb.12 for ; Sun, 09 Sep 2012 03:08:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=X7hqJ5l93z5y1AQEmq3bkL88XQI6RnZa3jBE21Pryz8=; b=firi6reOGIyMVJWFFD9LourMQVzmh7vxXaltejQqVDmoBpRU4iuqgbfyBhAwvDfifm 38mA+lrdkr/uDml+NMIgySzkpSfBMY8wAyXsl3KJsIAmXea+rM2Gx3hRrhKBZyQjGnvD bDZDlAn0EAEDpAM5UsarDWY7kL1zVWhTys0Lo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=X7hqJ5l93z5y1AQEmq3bkL88XQI6RnZa3jBE21Pryz8=; b=fUpNs9x3CYvGkDXF4qTXPq0Oe6PMn29aadEbfyHgiICsw4N2ngk6kZTYqGKUWlvlRm dneIWjne4Ms2VAU9QhSOnpL7IzAfZ2KBke6Msd0JtDp54YwaFSV11bOA+92rIzczf1gu AABYiESCt5tNNJD6i3NxeCT92xR50l0lFInkuSGY1WVwj+dG0GsyBuJ5N7VSxri+vZc7 6m8W0ty6u8LJH9DP+SayZnquxm11JieFe1vZ7ET6Rxt9Vu6oz3N7gZECe9R7KAjMZwrk +iXIsNMZuUx5KERaKSGWy18I/w2sYGlPeIv2x9V7SmJVuqcRcIu+f+Y2tB/2v8cFEtuK qVQw== Received: by 10.180.24.4 with SMTP id q4mr9623837wif.19.1347185294375; Sun, 09 Sep 2012 03:08:14 -0700 (PDT) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id o2sm15381282wiz.11.2012.09.09.03.08.12 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 03:08:13 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Sun, 9 Sep 2012 11:00:41 +0200 Message-Id: <1347181247-2484-2-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.2 In-Reply-To: <1347181247-2484-1-git-send-email-daniel.vetter@ffwll.ch> References: <1347181247-2484-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQk1ylEeWBlfokgV045egp22Isa6Dp3ghqKjy199zDIJEvApByR4S7Ezyw7Yjdr+/7teJVMf Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 2/8] drm/i915: extract gmbus_wait_hw_status X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org The gmbus interrupt generation is rather fiddly: We can only ever enable one interrupt source (but we always want to check for NAK in addition to the real bit). And the bits in the gmbus status register don't map at all to the bis in the irq register. To prepare for this mess, start by extracting the hw status wait loop into it's own function, consolidate the NAK error handling a bit. To keep things flexible, pass in the status bit we care about (in addition to any NAK signalling). v2: I've failed to notice that the sens of GMBUS_ACTIVE is inverted, Chris Wilson gladly pointed that out for me. To keep things simple, ignore that case for now (we only need to idle the gmbus controller at the end of an entire i2c transaction, not after every message). Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_i2c.c | 46 ++++++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index b9755f6..57decac 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -204,6 +204,24 @@ intel_gpio_setup(struct intel_gmbus *bus, u32 pin) } static int +gmbus_wait_hw_status(struct drm_i915_private *dev_priv, + u32 gmbus2_status) +{ + int ret; + int reg_offset = dev_priv->gpio_mmio_base; + u32 gmbus2; + + ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & + (GMBUS_SATOER | gmbus2_status), + 50); + + if (gmbus2 & GMBUS_SATOER) + return -ENXIO; + + return ret; +} + +static int gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, u32 gmbus1_index) { @@ -220,15 +238,10 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, while (len) { int ret; u32 val, loop = 0; - u32 gmbus2; - ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & - (GMBUS_SATOER | GMBUS_HW_RDY), - 50); + ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY); if (ret) - return -ETIMEDOUT; - if (gmbus2 & GMBUS_SATOER) - return -ENXIO; + return ret; val = I915_READ(GMBUS3 + reg_offset); do { @@ -262,7 +275,6 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); while (len) { int ret; - u32 gmbus2; val = loop = 0; do { @@ -271,13 +283,9 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) I915_WRITE(GMBUS3 + reg_offset, val); - ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & - (GMBUS_SATOER | GMBUS_HW_RDY), - 50); + ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY); if (ret) - return -ETIMEDOUT; - if (gmbus2 & GMBUS_SATOER) - return -ENXIO; + return ret; } return 0; } @@ -346,8 +354,6 @@ gmbus_xfer(struct i2c_adapter *adapter, I915_WRITE(GMBUS0 + reg_offset, bus->reg0); for (i = 0; i < num; i++) { - u32 gmbus2; - if (gmbus_is_index_read(msgs, i, num)) { ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); i += 1; /* set i to the index of the read xfer */ @@ -362,13 +368,11 @@ gmbus_xfer(struct i2c_adapter *adapter, if (ret == -ENXIO) goto clear_err; - ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & - (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), - 50); + ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE); + if (ret == -ENXIO) + goto clear_err; if (ret) goto timeout; - if (gmbus2 & GMBUS_SATOER) - goto clear_err; } /* Generate a STOP condition on the bus. Note that gmbus can't generata