From patchwork Sun Sep 9 09:00:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1427651 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id A4568DF264 for ; Sun, 9 Sep 2012 10:11:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A3FBF9EC2B for ; Sun, 9 Sep 2012 03:11:35 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 8801C9F51B for ; Sun, 9 Sep 2012 03:08:19 -0700 (PDT) Received: by weyr3 with SMTP id r3so664637wey.36 for ; Sun, 09 Sep 2012 03:08:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=fdXh9SjLZuA7mcRea1Z/fIx3/5jcqUMARkOVaERwF2E=; b=KV1IEQpKc0DULzvOogRgD/UbZd4mTznvVemLuxhbPmNNOO9AZh6nj5dym7fJ5dDiw7 L6Vm7HVfGg8QSjEyAH2ziERwOB03fwQ8SpnvXZ9t0bFyPJpt9+IFUOz0MsnpMZYRdsXt zoiR3ZZA+rZlF+I6Jdfv73MrlOo8rucg6WN9s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=fdXh9SjLZuA7mcRea1Z/fIx3/5jcqUMARkOVaERwF2E=; b=iA73CYCIUtQ5G3EZ0zEGJGInqZmKkzkUy9iiGr3HNX3Y5MADQv80t/dW6ukte0btDm yGI2cqGhgMGXDPMgtlkBvDUYCSqIQvjb2cT1rAXr6UnAl6rq5bCjCJsoSi+PEJJCr5Xr t7Sb6ygYjO9w7luwn28fmVAWrd2SiUa1VJIEv6qyOC75RklYjGDqi/BCbR4kLtT+kqRy ZwaRn3VyGk/L2rezADIzvGgBUh5Uvg5jWoarB6KErlZTBbe4StfEKpHvM2xs3eCgVUTZ aDE6kzgKAHcpyc4wxzui8O3LIKu6GPjJVt9nnITLdbP8Ua+tek3WDeFs/wbZ1yAUvV9m +adw== Received: by 10.180.107.103 with SMTP id hb7mr9711032wib.3.1347185298626; Sun, 09 Sep 2012 03:08:18 -0700 (PDT) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id o2sm15381282wiz.11.2012.09.09.03.08.17 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 03:08:17 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Sun, 9 Sep 2012 11:00:44 +0200 Message-Id: <1347181247-2484-5-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.2 In-Reply-To: <1347181247-2484-1-git-send-email-daniel.vetter@ffwll.ch> References: <1347181247-2484-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQlFTvfV1xOv5RqQ5eCrRvdEn64R1NvaH03lCTxxqrzTxLpBVFtl/2EOwxKqCt9VKvhyXWbO Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 5/8] drm/i915: use gmbus irq to wait for gmbus idle X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org GMBUS_ACTIVE has inverted sense and so doesn't fit into the wait_hw_status helper, hence create a new gmbus_wait_idle functions. Also, we only care about the idle irq event and nothing else, which allows us to use the wait_event_timeout helper directly without jumping through hoops to catch NAKs. Since gen2/3 don't have gmbus interrupts, handle them separately with the old wait_for macro. This shaves another few ms off reading EDID from a hdmi screen on my testbox here. EDID reading with interrupt driven gmbus is now as fast as with busy-looping gmbus at 28 ms here (with negligible cpu overhead). Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_i2c.c | 32 ++++++++++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 7413595..4a38a30 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -204,6 +204,7 @@ intel_gpio_setup(struct intel_gmbus *bus, u32 pin) algo->data = bus; } +#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 4) static int gmbus_wait_hw_status(struct drm_i915_private *dev_priv, u32 gmbus2_status, @@ -241,6 +242,31 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv, } static int +gmbus_wait_idle(struct drm_i915_private *dev_priv) +{ + int ret; + int reg_offset = dev_priv->gpio_mmio_base; + +#define C ((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0) + + if (!HAS_GMBUS_IRQ(dev_priv->dev)) + return wait_for(C, 10); + + /* Important: The hw handles only the first bit, so set only one! */ + I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); + + ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10); + + I915_WRITE(GMBUS4 + reg_offset, 0); + + if (ret) + return 0; + else + return -ETIMEDOUT; +#undef C +} + +static int gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, u32 gmbus1_index) { @@ -407,8 +433,7 @@ gmbus_xfer(struct i2c_adapter *adapter, * We will re-enable it at the start of the next xfer, * till then let it sleep. */ - if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, - 10)) { + if (gmbus_wait_idle(dev_priv)) { DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", adapter->name); ret = -ETIMEDOUT; @@ -432,8 +457,7 @@ clear_err: * it's slow responding and only answers on the 2nd retry. */ ret = -ENXIO; - if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, - 10)) { + if (gmbus_wait_idle(dev_priv)) { DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", adapter->name); ret = -ETIMEDOUT;