[3/3,HACK] fix ilk/gm45 dp dpms off/on cycles

Commit Message

Daniel Vetter Sept. 10, 2012, 7:58 p.m. UTC

Without this we have link train fail. Still need to figure out what
exactly we seem to lose, but without this dp on gm45 and pch dp on ilk
utterly fails in link retrainig at dpms on. The only way to fix this
is to do a full modeset (i.e. eseentially what this patch here does).

Not-Signed-Off-by: Daniel Vetter <[e-mail]>
---
 drivers/gpu/drm/i915/intel_display.c |   12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fcc7300..1aba63c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3438,6 +3438,12 @@  static void intel_crtc_update_sarea(struct drm_crtc *crtc,
 	}
 }
 
+static int intel_crtc_mode_set(struct drm_crtc *crtc,
+			       struct drm_display_mode *mode,
+			       struct drm_display_mode *adjusted_mode,
+			       int x, int y,
+			       struct drm_framebuffer *fb);
+
 /**
  * Sets the power management mode of the pipe and plane.
  */
@@ -3451,9 +3457,11 @@  void intel_crtc_update_dpms(struct drm_crtc *crtc)
 	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
 		enable |= intel_encoder->connectors_active;
 
-	if (enable)
+	if (enable) {
+		intel_crtc_mode_set(crtc, &crtc->mode, &crtc->hwmode,
+				    crtc->x, crtc->y, crtc->fb);
 		dev_priv->display.crtc_enable(crtc);
-	else
+	} else
 		dev_priv->display.crtc_disable(crtc);
 
 	intel_crtc_update_sarea(crtc, enable);