From patchwork Tue Sep 11 06:17:33 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1436231 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 261CC3FC33 for ; Tue, 11 Sep 2012 09:38:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1F9379EEB1 for ; Tue, 11 Sep 2012 02:38:35 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f171.google.com (mail-wi0-f171.google.com [209.85.212.171]) by gabe.freedesktop.org (Postfix) with ESMTP id 2F24C9E9E7 for ; Tue, 11 Sep 2012 00:25:02 -0700 (PDT) Received: by wibhq4 with SMTP id hq4so2745218wib.12 for ; Tue, 11 Sep 2012 00:25:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=q5DHyuO5yleFJ1zu6jBRjxWAB3/YiYzhtt+wNQR1hOE=; b=POKjX+KzWche1BcpG6a+Murpwxz6VHpQbIhUjay7HE61D1xXgxwTlceTBq0FuYvs30 bs4a4+57MCkAN9LwWmn+KE/V3Wji6k98Am+KDNID/wxTIX4hP1GXNNgO3+oqnPlkn3Td eWb6JKcTVTqZ8WDKMF5e3nVWaNfXXy2LLz2n4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=q5DHyuO5yleFJ1zu6jBRjxWAB3/YiYzhtt+wNQR1hOE=; b=UKXW1P4KUqAvRMubZusSBTdFiF2lFUwzJDShY9+9vAWj+AYzaYFmdkBRF4C74Cqd3M 5hOblWhC1Ks9E/19VfARb5ABUaxrinFvpzhUKEz+alSPShwNIV0Fdk/KVJvTZstFZp2+ BcGeRsLP72lHMaBqdV7PtuKjXs6iXE6gb3K3U1pMyxItw3dwDwtUHI9ArNwPdWo3N5kL GNt2zX/bk/We69/A61paN5GQxJ1M4J3X3tPK1kEHVcinz4GpRslbxB6XwJrWPy8osfSD O+e/aZSFVJG/YwK8mZR3X+2xxmM86sP0VnHWtpAO38wQrsF6wGOSdih3ojMSIp0vztkJ v4Lw== Received: by 10.180.24.4 with SMTP id q4mr22990726wif.19.1347348302222; Tue, 11 Sep 2012 00:25:02 -0700 (PDT) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id hv8sm1608398wib.0.2012.09.11.00.25.00 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 11 Sep 2012 00:25:01 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Tue, 11 Sep 2012 08:17:33 +0200 Message-Id: <1347344253-13698-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.2 In-Reply-To: <1347120892-1063-1-git-send-email-daniel.vetter@ffwll.ch> References: <1347120892-1063-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQmvBTR1zyDDg8dGmoOs5k7EGCc7yPuEAnZ3y65e2hQ6H7lDxfx6W6s+3RA4xQzEsvvV4C9s Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: fixup the plane->pipe fixup code X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org We need to check whether the _other plane is on our pipe, not whether our plane is on the other pipe. Otherwise if not both pipes/planes are active, we won't properly clean up the mess and set up our desired plane->pipe mapping. v2: Fixup the logic, I've totally fumbled it. Noticed by Chris Wilson. v3: I've checked Bspec, and the flexible plane->pipe mapping is a gen2/3 feature, so test for that instead of PCH_SPLIT Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51265 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49838 Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fd9c275..7454df6 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7994,11 +7994,27 @@ static void intel_enable_pipe_a(struct drm_device *dev) } +static bool +intel_check_plane_mapping(struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; + u32 reg, val; + + reg = DSPCNTR(!crtc->plane); + val = I915_READ(reg); + + if ((val & DISPLAY_PLANE_ENABLE) && + (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) + return false; + + return true; +} + static void intel_sanitize_crtc(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - u32 reg, val; + u32 reg; /* Clear any frame start delays used for debugging left by the BIOS */ reg = PIPECONF(crtc->pipe); @@ -8006,17 +8022,10 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) /* We need to sanitize the plane -> pipe mapping first because this will * disable the crtc (and hence change the state) if it is wrong. */ - if (!HAS_PCH_SPLIT(dev)) { + if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { struct intel_connector *connector; bool plane; - reg = DSPCNTR(crtc->plane); - val = I915_READ(reg); - - if ((val & DISPLAY_PLANE_ENABLE) == 0 && - (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) - goto ok; - DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", crtc->base.base.id); @@ -8040,7 +8049,6 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) WARN_ON(crtc->active); crtc->base.enabled = false; } -ok: if (dev_priv->quirks & QUIRK_PIPEA_FORCE && crtc->pipe == PIPE_A && !crtc->active) {