From patchwork Tue Sep 18 10:34:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 1471821 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 73A2F400EC for ; Tue, 18 Sep 2012 10:36:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 592F1A086D for ; Tue, 18 Sep 2012 03:36:31 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id 2BC42A01F9 for ; Tue, 18 Sep 2012 03:36:16 -0700 (PDT) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.73.22; Received: from arrandale.alporthouse.com (unverified [78.156.73.22]) by fireflyinternet.com (Firefly Internet SMTP) with ESMTP id 122510110-1500050 for multiple; Tue, 18 Sep 2012 11:36:09 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Tue, 18 Sep 2012 11:34:49 +0100 Message-Id: <1347964489-32570-1-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 1.7.10.4 X-Originating-IP: 78.156.73.22 Subject: [Intel-gfx] [PATCH] drm/i915: ioremap the right range for the registers on gen2 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Fixes regression from commit 1ca673954355eb4105ef7fccdd770e69d4d3d1ef Author: Chris Wilson Date: Fri Sep 14 11:57:46 2012 +0100 drm/i915: Limit the ioremap of the PCI bar to the registers which only mapped 64k of the register BAR when the full 512k was required. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_dma.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index f0cad84..5779e8f 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1524,13 +1524,15 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); - /* Restrict iomap to avoid clobbering the GTT which we want WC mapped. - * Do not attempt to map the whole BAR! - */ mmio_bar = IS_GEN2(dev) ? 1 : 0; - if (info->gen < 3) - mmio_size = 64*1024; - else if (info->gen < 5) + /* Before gen4, the registers and the GTT are behind different BARs. + * However, from gen4 onwards, the registers and the GTT are shared + * in the same BAR, so we want to restrict this ioremap from + * clobbering the GTT which we want ioremap_wc instead. Fortunately, + * the register BAR remains the same size for all the earlier + * generations up to Ironlake. + */ + if (info->gen < 5) mmio_size = 512*1024; else mmio_size = 2*1024*1024;