From patchwork Wed Sep 19 20:28:58 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 1480571 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 3BCC03FE65 for ; Wed, 19 Sep 2012 20:39:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 22C55A0AE0 for ; Wed, 19 Sep 2012 13:39:45 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from oproxy11-pub.bluehost.com (oproxy11-pub.bluehost.com [173.254.64.10]) by gabe.freedesktop.org (Postfix) with SMTP id 40CDFA0AAB for ; Wed, 19 Sep 2012 13:29:09 -0700 (PDT) Received: (qmail 20794 invoked by uid 0); 19 Sep 2012 20:29:08 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by oproxy11.bluehost.com with SMTP; 19 Sep 2012 20:29:08 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=JyhuIyXYsDG/NVgAGBrtzKd0tuRWllgjKY48fwnjlgI=; b=Mjo/PN2CQgGLKQJrPCkMf0tIsdb4pYlAzYPXosArrDI0XumDyYUqg3M5JueB1Nx4jcRi5E4rNh4qCRZxadagcCgiTVxdBZ+2jon1+imNOzP+VgwLRRT4MJL19HQ4T0N7; Received: from [67.161.37.189] (port=40760 helo=jbarnes-desktop.intel.com) by box514.bluehost.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.76) (envelope-from ) id 1TEQtM-0006BL-UM; Wed, 19 Sep 2012 14:29:05 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Wed, 19 Sep 2012 13:28:58 -0700 Message-Id: <1348086543-24427-4-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1348086543-24427-1-git-send-email-jbarnes@virtuousgeek.org> References: <1348086543-24427-1-git-send-email-jbarnes@virtuousgeek.org> X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH 4/9] drm/i915: add post-flush store dw workaround X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Several platforms need this to flush the CS write buffers. References: https://bugs.freedesktop.org/show_bug.cgi?id=50241 Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 55cdb4d..ef5101f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -216,7 +216,7 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, u32 flags = 0; struct pipe_control *pc = ring->private; u32 scratch_addr = pc->gtt_offset + 128; - int ret; + int ret, i; /* Force SNB workarounds for PIPE_CONTROL flushes */ ret = intel_emit_post_sync_nonzero_flush(ring); @@ -259,6 +259,19 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, intel_ring_emit(ring, 0); intel_ring_advance(ring); + ret = intel_ring_begin(ring, 4 * 8); + if (ret) + return ret; + + for (i = 0; i < 8; i++) { + intel_ring_emit(ring, MI_STORE_DWORD_INDEX); + intel_ring_emit(ring, I915_GEM_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT); + intel_ring_emit(ring, 0); + intel_ring_emit(ring, MI_NOOP); + } + intel_ring_advance(ring); + + return 0; }