| Message ID | 1348086543-24427-6-git-send-email-jbarnes@virtuousgeek.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Sep 19, 2012 at 01:29:00PM -0700, Jesse Barnes wrote: > Workaround for dual port PS dispatch on GT1. > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e570aea..e863973 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4249,6 +4249,10 @@ > #define GEN7_L3LOG_BASE 0xB070 > #define GEN7_L3LOG_SIZE 0x80 > > +#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ > +#define GEN7_HALF_SLICE_CHICKEN1_IVB 0xf100 > +#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) > + > #define G4X_AUD_VID_DID 0x62020 > #define INTEL_AUDIO_DEVCL 0x808629FB > #define INTEL_AUDIO_DEVBLC 0x80862801 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 372a398..f860cdd 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3537,6 +3537,17 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) > CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | > CHICKEN3_DGMG_DONE_FIX_DISABLE); > > + /* WaDisablePSDDualDispatchEnable */ > + if (dev->pci_device == 0x0156 || > + dev->pci_device == 0x0152) Can we please have a comment here explaining which pci ids we're matching here? Just in case we add yet another variant sometime. Or just plainly use IS_MOBILE, which seems to match here ... -Daniel > + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > + I915_READ(GEN7_HALF_SLICE_CHICKEN1) | > + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > + else > + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_IVB, > + I915_READ(GEN7_HALF_SLICE_CHICKEN1) | > + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > + > /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ > I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, > GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); > @@ -3618,6 +3629,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | > CHICKEN3_DGMG_DONE_FIX_DISABLE); > > + /* WaDisablePSDDualDispatchEnable */ > + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > + I915_READ(GEN7_HALF_SLICE_CHICKEN1) | > + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > + > /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ > I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, > GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Tue, Sep 25, 2012 at 9:51 AM, Daniel Vetter <daniel@ffwll.ch> wrote: > On Wed, Sep 19, 2012 at 01:29:00PM -0700, Jesse Barnes wrote: >> Workaround for dual port PS dispatch on GT1. >> >> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> >> + /* WaDisablePSDDualDispatchEnable */ >> + if (dev->pci_device == 0x0156 || >> + dev->pci_device == 0x0152) > > Can we please have a comment here explaining which pci ids we're matching > here? Just in case we add yet another variant sometime. Or just plainly > use IS_MOBILE, which seems to match here ... > -Daniel This looks like testing if we're running on an IVB GT1 device (and then we're missing 0x015a?). The address of the register is different on GT1 and GT2 devices.
On Mon, 1 Oct 2012 17:52:21 +0100 "Lespiau, Damien" <damien.lespiau@intel.com> wrote: > On Tue, Sep 25, 2012 at 9:51 AM, Daniel Vetter <daniel@ffwll.ch> wrote: > > On Wed, Sep 19, 2012 at 01:29:00PM -0700, Jesse Barnes wrote: > >> Workaround for dual port PS dispatch on GT1. > >> > >> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > >> + /* WaDisablePSDDualDispatchEnable */ > >> + if (dev->pci_device == 0x0156 || > >> + dev->pci_device == 0x0152) > > > > Can we please have a comment here explaining which pci ids we're matching > > here? Just in case we add yet another variant sometime. Or just plainly > > use IS_MOBILE, which seems to match here ... > > -Daniel > > This looks like testing if we're running on an IVB GT1 device (and > then we're missing 0x015a?). The address of the register is different > on GT1 and GT2 devices. > Yeah I have an updated version that uses IS_MOBILE since I think that matches the IDs we want. Jesse
On Wed, Sep 19, 2012 at 9:29 PM, Jesse Barnes <jbarnes@virtuousgeek.org> wrote: > Workaround for dual port PS dispatch on GT1. > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e570aea..e863973 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4249,6 +4249,10 @@ > #define GEN7_L3LOG_BASE 0xB070 > #define GEN7_L3LOG_SIZE 0x80 > > +#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ > +#define GEN7_HALF_SLICE_CHICKEN1_IVB 0xf100 > +#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) > + > #define G4X_AUD_VID_DID 0x62020 > #define INTEL_AUDIO_DEVCL 0x808629FB > #define INTEL_AUDIO_DEVBLC 0x80862801 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 372a398..f860cdd 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3537,6 +3537,17 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) > CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | > CHICKEN3_DGMG_DONE_FIX_DISABLE); > > + /* WaDisablePSDDualDispatchEnable */ > + if (dev->pci_device == 0x0156 || > + dev->pci_device == 0x0152) > + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > + I915_READ(GEN7_HALF_SLICE_CHICKEN1) | > + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > + else > + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_IVB, > + I915_READ(GEN7_HALF_SLICE_CHICKEN1) | > + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > + It looks like we don't need to force the single port dispatch on IVB GT2 devices, maybe just drop the else then? 0x015a is also a GT1 device that seems to be missing from the if. I guess it'd be nice to have an IS_IVB_GT1() macro there. Other than those 2 points the rest looks good to me: Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
On Mon, Oct 1, 2012 at 5:56 PM, Jesse Barnes <jbarnes@virtuousgeek.org> wrote: > Yeah I have an updated version that uses IS_MOBILE since I think that > matches the IDs we want. I don't think IS_MOBILE() is what we want here, IS_MOBILE() would be matching 0x0156 and 0x0166 while your code tests for 0x0156 and 0x0152 (and, to me, is missing 0x015a) which are GT1 devices (and the _IVB version of the register is valid for GT2 devices).
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e570aea..e863973 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4249,6 +4249,10 @@ #define GEN7_L3LOG_BASE 0xB070 #define GEN7_L3LOG_SIZE 0x80 +#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ +#define GEN7_HALF_SLICE_CHICKEN1_IVB 0xf100 +#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) + #define G4X_AUD_VID_DID 0x62020 #define INTEL_AUDIO_DEVCL 0x808629FB #define INTEL_AUDIO_DEVBLC 0x80862801 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 372a398..f860cdd 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3537,6 +3537,17 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | CHICKEN3_DGMG_DONE_FIX_DISABLE); + /* WaDisablePSDDualDispatchEnable */ + if (dev->pci_device == 0x0156 || + dev->pci_device == 0x0152) + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, + I915_READ(GEN7_HALF_SLICE_CHICKEN1) | + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); + else + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_IVB, + I915_READ(GEN7_HALF_SLICE_CHICKEN1) | + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); + /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); @@ -3618,6 +3629,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev) CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | CHICKEN3_DGMG_DONE_FIX_DISABLE); + /* WaDisablePSDDualDispatchEnable */ + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, + I915_READ(GEN7_HALF_SLICE_CHICKEN1) | + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); + /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
Workaround for dual port PS dispatch on GT1. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> --- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+)